drivers/perf/hisilicon/hisi_uncore_pmu.h

Source file repositories/reference/linux-study-clean/drivers/perf/hisilicon/hisi_uncore_pmu.h

File Facts

System
Linux kernel
Corpus path
drivers/perf/hisilicon/hisi_uncore_pmu.h
Extension
.h
Size
6315 bytes
Lines
175
Domain
Driver Families
Bucket
drivers/perf
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hisi_uncore_ops {
	int (*check_filter)(struct perf_event *event);
	void (*write_evtype)(struct hisi_pmu *, int, u32);
	int (*get_event_idx)(struct perf_event *);
	u64 (*read_counter)(struct hisi_pmu *, struct hw_perf_event *);
	void (*write_counter)(struct hisi_pmu *, struct hw_perf_event *, u64);
	void (*enable_counter)(struct hisi_pmu *, struct hw_perf_event *);
	void (*disable_counter)(struct hisi_pmu *, struct hw_perf_event *);
	void (*enable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
	void (*disable_counter_int)(struct hisi_pmu *, struct hw_perf_event *);
	void (*start_counters)(struct hisi_pmu *);
	void (*stop_counters)(struct hisi_pmu *);
	u32 (*get_int_status)(struct hisi_pmu *hisi_pmu);
	void (*clear_int_status)(struct hisi_pmu *hisi_pmu, int idx);
	void (*enable_filter)(struct perf_event *event);
	void (*disable_filter)(struct perf_event *event);
};

/* Describes the HISI PMU chip features information */
struct hisi_pmu_dev_info {
	const char *name;
	const struct attribute_group **attr_groups;
	u32 counter_bits;
	u32 check_event;
	void *private;
};

struct hisi_pmu_hwevents {
	struct perf_event *hw_events[HISI_MAX_COUNTERS];
	DECLARE_BITMAP(used_mask, HISI_MAX_COUNTERS);
	const struct attribute_group **attr_groups;
};

/**
 * struct hisi_pmu_topology - Describe the topology hierarchy on which the PMU
 *                            is located.
 * @sccl_id: ID of the SCCL on which the PMU locate is located.
 * @sicl_id: ID of the SICL on which the PMU locate is located.
 * @scl_id:  ID used by the core which is unaware of the SCCL/SICL.
 * @ccl_id: ID of the CCL (CPU cluster) on which the PMU is located.
 * @index_id: the ID of the PMU module if there're several PMUs at a
 *            particularly location in the topology.
 * @sub_id: submodule ID of the PMU. For example we use this for DDRC PMU v2
 *          since each DDRC has more than one DMC
 *
 * The ID will be -1 if the PMU isn't located on a certain topology.
 */
struct hisi_pmu_topology {
	/*
	 * SCCL (Super CPU CLuster) and SICL (Super I/O Cluster) are parallel
	 * so a PMU cannot locate on a SCCL and a SICL. If the SCCL/SICL
	 * distinction is not relevant, use scl_id instead.
	 */
	union {
		int sccl_id;
		int sicl_id;
		int scl_id;
	};
	int ccl_id;
	int index_id;
	int sub_id;
};

/* Generic pmu struct for different pmu types */
struct hisi_pmu {
	struct pmu pmu;
	const struct hisi_uncore_ops *ops;
	const struct hisi_pmu_dev_info *dev_info;
	struct hisi_pmu_hwevents pmu_events;
	struct hisi_pmu_topology topo;
	/*
	 * CPUs associated to the PMU and are preferred to use for counting.
	 * Could be empty if PMU has no association (e.g. PMU on SICL), in
	 * which case any online CPU will be used.
	 */
	cpumask_t associated_cpus;
	/* CPU used for counting */
	int on_cpu;
	int irq;
	struct device *dev;
	struct hlist_node node;
	void __iomem *base;
	int num_counters;
	int counter_bits;
	/* check event code range */
	int check_event;
	u32 identifier;
};

/* Generic implementation of cpumask/identifier group */

Annotation

Implementation Notes