drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

Source file repositories/reference/linux-study-clean/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c
Extension
.c
Size
16379 bytes
Lines
527
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018, Broadcom */

/*
 * This module contains USB PHY initialization for power up and S3 resume
 * for newer Synopsys based USB hardware first used on the bcm7216.
 */

#include <linux/delay.h>
#include <linux/io.h>

#include <linux/soc/brcmstb/brcmstb.h>
#include "phy-brcm-usb-init.h"

#define PHY_LOCK_TIMEOUT_MS 200

/* Register definitions for syscon piarbctl registers */
#define PIARBCTL_CAM			0x00
#define PIARBCTL_SPLITTER		0x04
#define PIARBCTL_MISC			0x08
#define   PIARBCTL_MISC_SATA_PRIORITY_MASK		GENMASK(3, 0)
#define   PIARBCTL_MISC_CAM0_MEM_PAGE_MASK		GENMASK(7, 4)
#define   PIARBCTL_MISC_CAM1_MEM_PAGE_MASK		GENMASK(11, 8)
#define   PIARBCTL_MISC_USB_MEM_PAGE_MASK		GENMASK(15, 12)
#define   PIARBCTL_MISC_USB_PRIORITY_MASK		GENMASK(19, 16)
#define   PIARBCTL_MISC_USB_4G_SDRAM_MASK		BIT(29)
#define   PIARBCTL_MISC_USB_SELECT_MASK			BIT(30)
#define   PIARBCTL_MISC_SECURE_MASK			BIT(31)

#define PIARBCTL_MISC_USB_ONLY_MASK		\
	(PIARBCTL_MISC_USB_SELECT_MASK |	\
	 PIARBCTL_MISC_USB_4G_SDRAM_MASK |	\
	 PIARBCTL_MISC_USB_PRIORITY_MASK |	\
	 PIARBCTL_MISC_USB_MEM_PAGE_MASK)

/* Register definitions for the USB CTRL block */
#define USB_CTRL_SETUP			0x00
#define   USB_CTRL_SETUP_IOC_MASK			BIT(4)
#define   USB_CTRL_SETUP_IPP_MASK			BIT(5)
#define   USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK		BIT(9)
#define   USB_CTRL_SETUP_SCB1_EN_MASK			BIT(14)
#define   USB_CTRL_SETUP_SCB2_EN_MASK			BIT(15)
#define   USB_CTRL_SETUP_tca_drv_sel_MASK		BIT(24)
#define   USB_CTRL_SETUP_STRAP_IPP_SEL_MASK		BIT(25)
#define USB_CTRL_USB_PM			0x04
#define   USB_CTRL_USB_PM_REF_S2_CLK_SWITCH_EN_MASK	BIT(1)
#define   USB_CTRL_USB_PM_UTMI_S2_CLK_SWITCH_EN_MASK	BIT(2)
#define   USB_CTRL_USB_PM_XHC_S2_CLK_SWITCH_EN_MASK	BIT(3)
#define   USB_CTRL_USB_PM_XHC_PME_EN_MASK		BIT(4)
#define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK		BIT(22)
#define   USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK		BIT(23)
#define   USB_CTRL_USB_PM_SOFT_RESET_MASK		BIT(30)
#define   USB_CTRL_USB_PM_USB_PWRDN_MASK		BIT(31)
#define USB_CTRL_USB_PM_STATUS		0x08
#define USB_CTRL_USB_DEVICE_CTL1	0x10
#define   USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK	GENMASK(1, 0)
#define USB_CTRL_TEST_PORT_CTL		0x30
#define   USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK		GENMASK(7, 0)
#define   USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_PME_GEN_MASK	0x0000002e
#define USB_CTRL_TP_DIAG1		0x34
#define   USB_CTLR_TP_DIAG1_wake_MASK			BIT(1)
#define USB_CTRL_CTLR_CSHCR		0x50
#define   USB_CTRL_CTLR_CSHCR_ctl_pme_en_MASK		BIT(18)
#define USB_CTRL_P0_U2PHY_CFG1		0x68
#define   USB_CTRL_P0_U2PHY_CFG1_COMMONONN_MASK		BIT(10)
#define USB_CTRL_P0_U2PHY_CFG2		0x6c
#define   USB_CTRL_P0_U2PHY_CFG2_TXVREFTUNE0_MASK	GENMASK(20, 17)
#define   USB_CTRL_P0_U2PHY_CFG2_TXVREFTUNE0_SHIFT	17
#define   USB_CTRL_P0_U2PHY_CFG2_TXRESTUNE0_MASK	GENMASK(24, 23)
#define   USB_CTRL_P0_U2PHY_CFG2_TXRESTUNE0_SHIFT	23
#define   USB_CTRL_P0_U2PHY_CFG2_TXPREEMPAMPTUNE0_MASK	GENMASK(26, 25)
#define   USB_CTRL_P0_U2PHY_CFG2_TXPREEMPAMPTUNE0_SHIFT	25

/* Register definitions for the USB_PHY block in 7211b0 */
#define USB_PHY_PLL_CTL			0x00
#define   USB_PHY_PLL_CTL_PLL_SUSPEND_MASK		BIT(27)
#define   USB_PHY_PLL_CTL_PLL_RESETB_MASK		BIT(30)
#define USB_PHY_PLL_LDO_CTL		0x08
#define   USB_PHY_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK	BIT(0)
#define   USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK	BIT(1)
#define   USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK		BIT(2)
#define USB_PHY_UTMI_CTL_1		0x04
#define   USB_PHY_UTMI_CTL_1_PHY_MODE_MASK		GENMASK(3, 2)
#define   USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT		2
#define   USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK	BIT(11)
#define USB_PHY_IDDQ			0x1c
#define   USB_PHY_IDDQ_phy_iddq_MASK			BIT(0)
#define USB_PHY_STATUS			0x20
#define   USB_PHY_STATUS_pll_lock_MASK			BIT(0)

Annotation

Implementation Notes