drivers/phy/cadence/phy-cadence-salvo.c

Source file repositories/reference/linux-study-clean/drivers/phy/cadence/phy-cadence-salvo.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/cadence/phy-cadence-salvo.c
Extension
.c
Size
12550 bytes
Lines
398
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cdns_reg_pairs {
	u16 val;
	u32 off;
};

struct cdns_salvo_data {
	u8 reg_offset_shift;
	const struct cdns_reg_pairs *init_sequence_val;
	u8 init_sequence_length;
};

struct cdns_salvo_phy {
	struct phy *phy;
	struct clk *clk;
	void __iomem *base;
	struct cdns_salvo_data *data;
	enum usb2_disconn_threshold usb2_disconn;
};

static const struct of_device_id cdns_salvo_phy_of_match[];
static const struct cdns_salvo_data cdns_nxp_salvo_data;

static bool cdns_is_nxp_phy(struct cdns_salvo_phy *salvo_phy)
{
	return salvo_phy->data == &cdns_nxp_salvo_data;
}

static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 offset, u32 reg)
{
	return (u16)readl(salvo_phy->base + offset +
		reg * (1 << salvo_phy->data->reg_offset_shift));
}

static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, u32 offset,
			     u32 reg, u16 val)
{
	writel(val, salvo_phy->base + offset +
		reg * (1 << salvo_phy->data->reg_offset_shift));
}

/*
 * Below bringup sequence pair are from Cadence PHY's User Guide
 * and NXP platform tuning results.
 */
static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
	{0x0830, PHY_PMA_CMN_CTRL1},
	{0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
	{0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
	{0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
	{0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
	{0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
	{0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
	{0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
	{0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
	{0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
	{0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
	{0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
	{0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
	{0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
	{0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
	{0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
	{0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
	{0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
	{0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
	{0xbefc, TB_ADDR_XCVR_PSM_RCTRL},

	{0x7799, TB_ADDR_TX_PSC_A0},
	{0x7798, TB_ADDR_TX_PSC_A1},
	{0x509b, TB_ADDR_TX_PSC_A2},
	{0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
	{0x509b, TB_ADDR_TX_PSC_A3},
	{0x2090, TB_ADDR_TX_PSC_CAL},
	{0x2090, TB_ADDR_TX_PSC_RDY},

	{0xA6FD, TB_ADDR_RX_PSC_A0},
	{0xA6FD, TB_ADDR_RX_PSC_A1},
	{0xA410, TB_ADDR_RX_PSC_A2},
	{0x2410, TB_ADDR_RX_PSC_A3},

	{0x23FF, TB_ADDR_RX_PSC_CAL},
	{0x2010, TB_ADDR_RX_PSC_RDY},

	{0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
	{0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
	{0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
	{0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
	{0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
	{0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
	{0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
	{0x0480, TB_ADDR_RX_DIAG_BS_TM},

Annotation

Implementation Notes