drivers/phy/eswin/phy-eic7700-sata.c

Source file repositories/reference/linux-study-clean/drivers/phy/eswin/phy-eic7700-sata.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/eswin/phy-eic7700-sata.c
Extension
.c
Size
7904 bytes
Lines
274
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct eic7700_sata_phy {
	u32 tx_amplitude_tuning_val[3];
	u32 tx_preemph_tuning_val[3];
	struct reset_control *rst;
	struct regmap *regmap;
	struct clk *clk;
	struct phy *phy;
};

static const struct regmap_config eic7700_sata_phy_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = SATA_LOS_IDEN,
};

static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
			      u32 status)
{
	u32 val;
	int ret;

	ret = regmap_read_poll_timeout(regmap, reg, val,
				       (val & checkbit) == status,
				       PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);

	return ret;
}

static int eic7700_sata_phy_init(struct phy *phy)
{
	struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
	u32 val;
	int ret;

	ret = clk_prepare_enable(sata_phy->clk);
	if (ret)
		return ret;

	regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);

	val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK,
			 sata_phy->tx_amplitude_tuning_val[0]) |
	      FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK,
			 sata_phy->tx_amplitude_tuning_val[1]) |
	      FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK,
			 sata_phy->tx_amplitude_tuning_val[2]);
	regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);

	val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK,
			 sata_phy->tx_preemph_tuning_val[0]) |
	      FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK,
			 sata_phy->tx_preemph_tuning_val[1]) |
	      FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK,
			 sata_phy->tx_preemph_tuning_val[2]);
	regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);

	val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
	      FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
	regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);

	val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
	regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);

	val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
	regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);

	val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
	regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);

	usleep_range(15, 20);

	ret = reset_control_deassert(sata_phy->rst);
	if (ret)
		goto disable_clk;

	ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
				 SATA_P0_PHY_READY, 1);
	if (ret < 0) {
		dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
		goto disable_clk;
	}

	return 0;

disable_clk:
	clk_disable_unprepare(sata_phy->clk);
	return ret;
}

Annotation

Implementation Notes