drivers/phy/freescale/phy-fsl-samsung-hdmi.c

File Facts

System

Linux kernel

Corpus path

drivers/phy/freescale/phy-fsl-samsung-hdmi.c

Extension

.c

Size

20888 bytes

Lines

744

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/bitfield.h
• linux/bits.h
• linux/clk.h
• linux/clk-provider.h
• linux/delay.h
• linux/iopoll.h
• linux/module.h
• linux/platform_device.h
• linux/pm_runtime.h

Detected Declarations

• struct phy_config
• struct reg_settings
• struct fsl_samsung_hdmi_phy
• function to_fsl_samsung_hdmi_phy
• function fsl_samsung_hdmi_phy_configure_pll_lock_det
• function fsl_samsung_hdmi_phy_find_pms
• function fsl_samsung_hdmi_phy_configure
• function phy_clk_recalc_rate
• function fsl_samsung_hdmi_calculate_phy
• function abs
• function fsl_samsung_hdmi_phy_clk_determine_rate
• function fsl_samsung_hdmi_phy_clk_set_rate
• function phy_clk_register
• function fsl_samsung_hdmi_phy_probe
• function fsl_samsung_hdmi_phy_remove
• function fsl_samsung_hdmi_phy_suspend
• function fsl_samsung_hdmi_phy_resume

Annotated Snippet

struct phy_config {
	u32	pixclk;
	u8	pll_div_regs[PHY_PLL_DIV_REGS_NUM];
};

/*
 * The calculated_phy_pll_cfg only handles integer divider for PMS,
 * meaning the last four entries will be fixed, but the first three will
 * be calculated by the PMS calculator.
 */
static struct phy_config calculated_phy_pll_cfg = {
	.pixclk = 0,
	.pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 },
};

/* The lookup table contains values for which the fractional divder is used */
static const struct phy_config phy_pll_cfg[] = {
	{
		.pixclk = 22250000,
		.pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },
	}, {
		.pixclk = 23750000,
		.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
	}, {
		.pixclk = 24024000,
		.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
	}, {
		.pixclk = 25175000,
		.pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
	},  {
		.pixclk = 26750000,
		.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
	},  {
		.pixclk = 27027000,
		.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
	}, {
		.pixclk = 29500000,
		.pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },
	}, {
		.pixclk = 30750000,
		.pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },
	}, {
		.pixclk = 30888000,
		.pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },
	}, {
		.pixclk = 33750000,
		.pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },
	}, {
		.pixclk = 35000000,
		.pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
	},  {
		.pixclk = 36036000,
		.pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
	}, {
		.pixclk = 43243200,
		.pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
	}, {
		.pixclk = 44500000,
		.pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },
	}, {
		.pixclk = 47000000,
		.pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },
	}, {
		.pixclk = 47500000,
		.pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },
	}, {
		.pixclk = 50349650,
		.pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
	}, {
		.pixclk = 53250000,
		.pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
	}, {
		.pixclk = 53500000,
		.pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
	},  {
		.pixclk = 54054000,
		.pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
	}, {
		.pixclk = 59000000,
		.pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },
	}, {
		.pixclk = 59340659,
		.pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
	},  {
		.pixclk = 61500000,
		.pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
	}, {
		.pixclk = 63500000,
		.pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },
	}, {

Annotation

• Immediate include surface: `linux/bitfield.h`, `linux/bits.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/delay.h`, `linux/iopoll.h`, `linux/module.h`, `linux/platform_device.h`.
• Detected declarations: `struct phy_config`, `struct reg_settings`, `struct fsl_samsung_hdmi_phy`, `function to_fsl_samsung_hdmi_phy`, `function fsl_samsung_hdmi_phy_configure_pll_lock_det`, `function fsl_samsung_hdmi_phy_find_pms`, `function fsl_samsung_hdmi_phy_configure`, `function phy_clk_recalc_rate`, `function fsl_samsung_hdmi_calculate_phy`, `function abs`.
• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.