drivers/phy/hisilicon/phy-hi3670-pcie.c

Source file repositories/reference/linux-study-clean/drivers/phy/hisilicon/phy-hi3670-pcie.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/hisilicon/phy-hi3670-pcie.c
Extension
.c
Size
22486 bytes
Lines
851
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hi3670_pcie_phy {
	struct device	*dev;
	void __iomem	*base;
	struct regmap	*apb;
	struct regmap	*crgctrl;
	struct regmap	*sysctrl;
	struct regmap	*pmctrl;
	struct clk	*apb_sys_clk;
	struct clk	*apb_phy_clk;
	struct clk	*phy_ref_clk;
	struct clk	*aclk;
	struct clk	*aux_clk;
	u32		eye_param[NUM_EYEPARAM];
};

/* Registers in PCIePHY */
static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
					 u32 reg)
{
	writel(val, phy->base + APB_PHY_START_ADDR + reg);
}

static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
{
	return readl(phy->base + APB_PHY_START_ADDR + reg);
}

static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
					  u32 val, u32 mask, u32 reg)
{
	u32 regval;

	regval = hi3670_apb_phy_readl(phy, reg);
	regval &= ~mask;
	regval |= val;
	hi3670_apb_phy_writel(phy, regval, reg);
}

static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
						u32 val, u32 reg)
{
	writel(val, phy->base + reg);
}

static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
					      u32 reg)
{
	return readl(phy->base + reg);
}

static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
{
	u32 val;

	regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
	val |= PCIE_DEBOUNCE_PARAM;
	if (enable)
		val &= ~PCIE_OE_BYPASS;
	else
		val |= PCIE_OE_BYPASS;
	regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
}

static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
{
	struct device *dev = phy->dev;
	struct device_node *np;
	int ret, i;

	np = dev->of_node;

	ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
					 phy->eye_param, NUM_EYEPARAM);
	if (!ret)
		return;

	/* There's no optional eye_param property. Set array to default */
	for (i = 0; i < NUM_EYEPARAM; i++)
		phy->eye_param[i] = EYEPARAM_NOCFG;
}

static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
{
	u32 val;

	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);

	if (phy->eye_param[1] != EYEPARAM_NOCFG) {
		val &= ~EYE_PARM1_MASK;
		val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);

Annotation

Implementation Notes