drivers/phy/intel/phy-intel-lgm-combo.c

Source file repositories/reference/linux-study-clean/drivers/phy/intel/phy-intel-lgm-combo.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/intel/phy-intel-lgm-combo.c
Extension
.c
Size
14392 bytes
Lines
618
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct intel_cbphy_iphy {
	struct phy		*phy;
	struct intel_combo_phy	*parent;
	struct reset_control	*app_rst;
	u32			id;
};

struct intel_combo_phy {
	struct device		*dev;
	struct clk		*core_clk;
	unsigned long		clk_rate;
	void __iomem		*app_base;
	void __iomem		*cr_base;
	struct regmap		*syscfg;
	struct regmap		*hsiocfg;
	u32			id;
	u32			bid;
	struct reset_control	*phy_rst;
	struct reset_control	*core_rst;
	struct intel_cbphy_iphy	iphy[PHY_MAX_NUM];
	enum intel_phy_mode	phy_mode;
	enum aggregated_mode	aggr_mode;
	u32			init_cnt;
	struct mutex		lock;
};

static int intel_cbphy_iphy_enable(struct intel_cbphy_iphy *iphy, bool set)
{
	struct intel_combo_phy *cbphy = iphy->parent;
	u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id);
	u32 val;

	/* Register: 0 is enable, 1 is disable */
	val = set ? 0 : mask;

	return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid),
				  mask, val);
}

static int intel_cbphy_pcie_refclk_cfg(struct intel_cbphy_iphy *iphy, bool set)
{
	struct intel_combo_phy *cbphy = iphy->parent;
	u32 mask = BIT(cbphy->id * 2 + iphy->id);
	u32 val;

	/* Register: 0 is enable, 1 is disable */
	val = set ? 0 : mask;

	return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, mask, val);
}

static inline void combo_phy_w32_off_mask(void __iomem *base, unsigned int reg,
					  u32 mask, u32 val)
{
	u32 reg_val;

	reg_val = readl(base + reg);
	reg_val &= ~mask;
	reg_val |= val;
	writel(reg_val, base + reg);
}

static int intel_cbphy_iphy_cfg(struct intel_cbphy_iphy *iphy,
				int (*phy_cfg)(struct intel_cbphy_iphy *))
{
	struct intel_combo_phy *cbphy = iphy->parent;
	int ret;

	ret = phy_cfg(iphy);
	if (ret)
		return ret;

	if (cbphy->aggr_mode != PHY_DL_MODE)
		return 0;

	return phy_cfg(&cbphy->iphy[PHY_1]);
}

static int intel_cbphy_pcie_en_pad_refclk(struct intel_cbphy_iphy *iphy)
{
	struct intel_combo_phy *cbphy = iphy->parent;
	int ret;

	ret = intel_cbphy_pcie_refclk_cfg(iphy, true);
	if (ret) {
		dev_err(cbphy->dev, "Failed to enable PCIe pad refclk\n");
		return ret;
	}

	if (cbphy->init_cnt)

Annotation

Implementation Notes