drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c

Source file repositories/reference/linux-study-clean/drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
Extension
.c
Size
13303 bytes
Lines
494
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ltq_vrx200_pcie_phy_priv {
	struct phy			*phy;
	unsigned int			mode;
	struct device			*dev;
	struct regmap			*phy_regmap;
	struct regmap			*rcu_regmap;
	struct clk			*pdi_clk;
	struct clk			*phy_clk;
	struct reset_control		*phy_reset;
	struct reset_control		*pcie_reset;
	u32				rcu_ahb_endian_offset;
	u32				rcu_ahb_endian_big_endian_mask;
};

static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
{
	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);

	/* PLL Setting */
	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);

	/* increase the bias reference voltage */
	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);

	/* Endcnt */
	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
			   PCIE_PHY_TX1_CTRL1_FORCE_EN,
			   PCIE_PHY_TX1_CTRL1_FORCE_EN);

	/* predrv_ser_en */
	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);

	/* ctrl_lim */
	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);

	/* ctrl */
	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);

	/* predrv_ser_en */
	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
			   0x4700);

	/* RTERM */
	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);

	/* Improved 100MHz clock output  */
	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);

	/* Reduced CDR BW to avoid glitches */
	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
}

static void pcie_phy_36mhz_mode_setup(struct phy *phy)
{
	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
			   PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
			   PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
			   PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
			   PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
			   PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
			   FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
			   PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);

	/* const_sdm */
	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);

	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
			   PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
			   FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
				      0xee));

Annotation

Implementation Notes