drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

Source file repositories/reference/linux-study-clean/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
Extension
.c
Size
7936 bytes
Lines
228
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Chunhui Dai <chunhui.dai@mediatek.com>
 */

#include "phy-mtk-hdmi.h"
#include "phy-mtk-io.h"

#define HDMI_CON0	0x00
#define RG_HDMITX_DRV_IBIAS_MASK	GENMASK(5, 0)
#define RG_HDMITX_EN_SER_MASK		GENMASK(15, 12)
#define RG_HDMITX_EN_SLDO_MASK		GENMASK(19, 16)
#define RG_HDMITX_EN_PRED_MASK		GENMASK(23, 20)
#define RG_HDMITX_EN_IMP_MASK		GENMASK(27, 24)
#define RG_HDMITX_EN_DRV_MASK		GENMASK(31, 28)

#define HDMI_CON1	0x04
#define RG_HDMITX_PRED_IBIAS_MASK	GENMASK(21, 18)
#define RG_HDMITX_PRED_IMP		BIT(22)
#define RG_HDMITX_DRV_IMP_MASK		GENMASK(31, 26)

#define HDMI_CON2	0x08
#define RG_HDMITX_EN_TX_CKLDO		BIT(0)
#define RG_HDMITX_EN_TX_POSDIV		BIT(1)
#define RG_HDMITX_TX_POSDIV_MASK	GENMASK(4, 3)
#define RG_HDMITX_EN_MBIAS		BIT(6)
#define RG_HDMITX_MBIAS_LPF_EN		BIT(7)

#define HDMI_CON4	0x10
#define RG_HDMITX_RESERVE_MASK		GENMASK(31, 0)

#define HDMI_CON6	0x18
#define RG_HTPLL_BR_MASK		GENMASK(1, 0)
#define RG_HTPLL_BC_MASK		GENMASK(3, 2)
#define RG_HTPLL_BP_MASK		GENMASK(7, 4)
#define RG_HTPLL_IR_MASK		GENMASK(11, 8)
#define RG_HTPLL_IC_MASK		GENMASK(15, 12)
#define RG_HTPLL_POSDIV_MASK		GENMASK(17, 16)
#define RG_HTPLL_PREDIV_MASK		GENMASK(19, 18)
#define RG_HTPLL_FBKSEL_MASK		GENMASK(21, 20)
#define RG_HTPLL_RLH_EN			BIT(22)
#define RG_HTPLL_FBKDIV_MASK		GENMASK(30, 24)
#define RG_HTPLL_EN			BIT(31)

#define HDMI_CON7	0x1c
#define RG_HTPLL_AUTOK_EN		BIT(23)
#define RG_HTPLL_DIVEN_MASK		GENMASK(30, 28)

static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
	void __iomem *base = hdmi_phy->regs;

	mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
	usleep_range(80, 100);
	mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
	usleep_range(80, 100);
	mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
	mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
	usleep_range(80, 100);
	return 0;
}

static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
{
	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
	void __iomem *base = hdmi_phy->regs;

	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
	usleep_range(80, 100);
	mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
	usleep_range(80, 100);
	mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
	mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
	mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
	usleep_range(80, 100);

Annotation

Implementation Notes