drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
Source file repositories/reference/linux-study-clean/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c- Extension
.c- Size
- 8991 bytes
- Lines
- 255
- Domain
- Driver Families
- Bucket
- drivers/phy
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
phy-mtk-hdmi.hphy-mtk-io.h
Detected Declarations
function Copyrightfunction mtk_hdmi_pll_unpreparefunction mtk_hdmi_pll_determine_ratefunction mtk_hdmi_pll_set_ratefunction mtk_hdmi_pll_recalc_ratefunction mtk_hdmi_phy_enable_tmdsfunction mtk_hdmi_phy_disable_tmds
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Jie Qiu <jie.qiu@mediatek.com>
*/
#include "phy-mtk-hdmi.h"
#include "phy-mtk-io.h"
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
#define RG_HDMITX_PLL_IR GENMASK(15, 12)
#define RG_HDMITX_PLL_IC GENMASK(11, 8)
#define RG_HDMITX_PLL_BP GENMASK(7, 4)
#define RG_HDMITX_PLL_BR GENMASK(3, 2)
#define RG_HDMITX_PLL_BC GENMASK(1, 0)
#define HDMI_CON1 0x04
#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
#define RG_HDMITX_PLL_BAND GENMASK(21, 16)
#define RG_HDMITX_PLL_REF_SEL BIT(15)
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
#define RG_HDMITX_PLL_TST_EN BIT(5)
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)
#define HDMI_CON2 0x08
#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
#define HDMI_CON3 0x0c
#define RG_HDMITX_SER_EN GENMASK(31, 28)
#define RG_HDMITX_PRD_EN GENMASK(27, 24)
#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
#define RG_HDMITX_DRV_EN GENMASK(19, 16)
#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
#define RG_HDMITX_SER_BIST_TOG BIT(2)
#define RG_HDMITX_SER_DIN_TOG BIT(1)
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
#define HDMI_CON4 0x10
#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)
#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
#define HDMI_CON5 0x14
#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
#define HDMI_CON6 0x18
#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
#define HDMI_CON7 0x1c
#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
#define RG_HDMITX_SER_DIN GENMASK(25, 16)
#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)
#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)
#define RG_HDMITX_RESERVE GENMASK(7, 0)
#define HDMI_CON8 0x20
#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)
#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)
#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)
#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)
#define RGS_HDMITX_PLUG_TST BIT(0)
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
void __iomem *base = hdmi_phy->regs;
Annotation
- Immediate include surface: `phy-mtk-hdmi.h`, `phy-mtk-io.h`.
- Detected declarations: `function Copyright`, `function mtk_hdmi_pll_unprepare`, `function mtk_hdmi_pll_determine_rate`, `function mtk_hdmi_pll_set_rate`, `function mtk_hdmi_pll_recalc_rate`, `function mtk_hdmi_phy_enable_tmds`, `function mtk_hdmi_phy_disable_tmds`.
- Atlas domain: Driver Families / drivers/phy.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.