drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

Source file repositories/reference/linux-study-clean/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
Extension
.c
Size
8951 bytes
Lines
295
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: jitao.shi <jitao.shi@mediatek.com>
 */

#include "phy-mtk-io.h"
#include "phy-mtk-mipi-dsi.h"

#define MIPITX_DSI_CON		0x00
#define RG_DSI_LDOCORE_EN		BIT(0)
#define RG_DSI_CKG_LDOOUT_EN		BIT(1)
#define RG_DSI_BCLK_SEL			GENMASK(3, 2)
#define RG_DSI_LD_IDX_SEL		GENMASK(6, 4)
#define RG_DSI_PHYCLK_SEL		GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL		BIT(10)
#define RG_DSI_LPTX_CLMP_EN		BIT(11)

#define MIPITX_DSI_CLOCK_LANE	0x04
#define MIPITX_DSI_DATA_LANE0	0x08
#define MIPITX_DSI_DATA_LANE1	0x0c
#define MIPITX_DSI_DATA_LANE2	0x10
#define MIPITX_DSI_DATA_LANE3	0x14
#define RG_DSI_LNTx_LDOOUT_EN		BIT(0)
#define RG_DSI_LNTx_CKLANE_EN		BIT(1)
#define RG_DSI_LNTx_LPTX_IPLUS1		BIT(2)
#define RG_DSI_LNTx_LPTX_IPLUS2		BIT(3)
#define RG_DSI_LNTx_LPTX_IMINUS		BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS		BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS		BIT(6)
#define RG_DSI_LNTx_RT_CODE		GENMASK(11, 8)

#define MIPITX_DSI_TOP_CON	0x40
#define RG_DSI_LNT_INTR_EN		BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN		BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN		BIT(2)
#define RG_DSI_LNT_TESTMODE_EN		BIT(3)
#define RG_DSI_LNT_IMP_CAL_CODE		GENMASK(7, 4)
#define RG_DSI_LNT_AIO_SEL		GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN		BIT(11)
#define RG_DSI_DEBUG_INPUT_EN		BIT(12)
#define RG_DSI_PRESERVE			GENMASK(15, 13)

#define MIPITX_DSI_BG_CON	0x44
#define RG_DSI_BG_CORE_EN		BIT(0)
#define RG_DSI_BG_CKEN			BIT(1)
#define RG_DSI_BG_DIV			GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE		BIT(4)

#define RG_DSI_V12_SEL			GENMASK(7, 5)
#define RG_DSI_V10_SEL			GENMASK(10, 8)
#define RG_DSI_V072_SEL			GENMASK(13, 11)
#define RG_DSI_V04_SEL			GENMASK(16, 14)
#define RG_DSI_V032_SEL			GENMASK(19, 17)
#define RG_DSI_V02_SEL			GENMASK(22, 20)
#define RG_DSI_VOUT_MSK			\
		(RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
		 RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
#define RG_DSI_BG_R1_TRIM		GENMASK(27, 24)
#define RG_DSI_BG_R2_TRIM		GENMASK(31, 28)

#define MIPITX_DSI_PLL_CON0	0x50
#define RG_DSI_MPPLL_PLL_EN		BIT(0)
#define RG_DSI_MPPLL_PREDIV		GENMASK(2, 1)
#define RG_DSI_MPPLL_TXDIV0		GENMASK(4, 3)
#define RG_DSI_MPPLL_TXDIV1		GENMASK(6, 5)
#define RG_DSI_MPPLL_POSDIV		GENMASK(9, 7)
#define RG_DSI_MPPLL_DIV_MSK		\
		(RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
		 RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN		BIT(10)
#define RG_DSI_MPPLL_MONREF_EN		BIT(11)
#define RG_DSI_MPPLL_VOD_EN		BIT(12)

#define MIPITX_DSI_PLL_CON1	0x54
#define RG_DSI_MPPLL_SDM_FRA_EN		BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT	BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN		BIT(2)
#define RG_DSI_MPPLL_SDM_SSC_PRD	GENMASK(31, 16)

#define MIPITX_DSI_PLL_CON2	0x58

#define MIPITX_DSI_PLL_TOP	0x64
#define RG_DSI_MPPLL_PRESERVE		GENMASK(15, 8)

#define MIPITX_DSI_PLL_PWR	0x68
#define RG_DSI_MPPLL_SDM_PWR_ON		BIT(0)
#define RG_DSI_MPPLL_SDM_ISO_EN		BIT(1)
#define RG_DSI_MPPLL_SDM_PWR_ACK	BIT(8)

Annotation

Implementation Notes