drivers/phy/microchip/lan966x_serdes.c

Source file repositories/reference/linux-study-clean/drivers/phy/microchip/lan966x_serdes.c

File Facts

System: Linux kernel
Corpus path: drivers/phy/microchip/lan966x_serdes.c
Extension: .c
Size: 17000 bytes
Lines: 626
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/err.h
linux/module.h
linux/of.h
linux/of_platform.h
linux/phy.h
linux/phy/phy.h
linux/platform_device.h
dt-bindings/phy/phy-lan966x-serdes.h
lan966x_serdes_regs.h

Detected Declarations

struct serdes_mux
struct serdes_ctrl
struct serdes_macro
struct lan966x_sd6g40_setup_args
struct lan966x_sd6g40_mode_args
struct lan966x_sd6g40_setup
enum lan966x_sd6g40_mode
enum lan966x_sd6g40_ltx2rx
function lan_rmw_
function lan966x_sd6g40_reg_cfg
function lan966x_sd6g40_get_conf_from_mode
function lan966x_calc_sd6g40_setup_lane
function lan966x_sd6g40_setup_lane
function lan966x_sd6g40_setup
function lan966x_rgmii_setup
function serdes_set_speed
function serdes_set_mode
function serdes_phy_create
function serdes_probe

Annotated Snippet

struct serdes_mux {
	u8			idx;
	u8			port;
	enum phy_mode		mode;
	int			submode;
	u32			mask;
	u32			mux;
};

static const struct serdes_mux lan966x_serdes_muxes[] = {
	SERDES_MUX_QSGMII(SERDES6G(1), 0, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
	SERDES_MUX_QSGMII(SERDES6G(1), 1, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
	SERDES_MUX_QSGMII(SERDES6G(1), 2, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
	SERDES_MUX_QSGMII(SERDES6G(1), 3, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),

	SERDES_MUX_QSGMII(SERDES6G(2), 4, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
	SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
	SERDES_MUX_QSGMII(SERDES6G(2), 6, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
	SERDES_MUX_QSGMII(SERDES6G(2), 7, HSIO_HW_CFG_QSGMII_ENA,
			  HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),

	SERDES_MUX_GMII(CU(0), 0, HSIO_HW_CFG_GMII_ENA,
			HSIO_HW_CFG_GMII_ENA_SET(BIT(0))),
	SERDES_MUX_GMII(CU(1), 1, HSIO_HW_CFG_GMII_ENA,
			HSIO_HW_CFG_GMII_ENA_SET(BIT(1))),

	SERDES_MUX_SGMII(SERDES6G(0), 0, HSIO_HW_CFG_SD6G_0_CFG, 0),
	SERDES_MUX_SGMII(SERDES6G(1), 1, HSIO_HW_CFG_SD6G_1_CFG, 0),
	SERDES_MUX_SGMII(SERDES6G(0), 2, HSIO_HW_CFG_SD6G_0_CFG,
			 HSIO_HW_CFG_SD6G_0_CFG_SET(1)),
	SERDES_MUX_SGMII(SERDES6G(1), 3, HSIO_HW_CFG_SD6G_1_CFG,
			 HSIO_HW_CFG_SD6G_1_CFG_SET(1)),

	SERDES_MUX_SGMII(SERDES6G(2), 4, 0, 0),

	SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
			 HSIO_HW_CFG_RGMII_ENA |
			 HSIO_HW_CFG_GMII_ENA,
			 HSIO_HW_CFG_RGMII_0_CFG_SET(0) |
			 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) |
			 HSIO_HW_CFG_GMII_ENA_SET(BIT(2))),
	SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
			 HSIO_HW_CFG_RGMII_ENA |
			 HSIO_HW_CFG_GMII_ENA,
			 HSIO_HW_CFG_RGMII_1_CFG_SET(0) |
			 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) |
			 HSIO_HW_CFG_GMII_ENA_SET(BIT(3))),
	SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
			 HSIO_HW_CFG_RGMII_ENA |
			 HSIO_HW_CFG_GMII_ENA,
			 HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
			 HSIO_HW_CFG_RGMII_ENA_SET(BIT(0)) |
			 HSIO_HW_CFG_GMII_ENA_SET(BIT(5))),
	SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
			 HSIO_HW_CFG_RGMII_ENA |
			 HSIO_HW_CFG_GMII_ENA,
			 HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
			 HSIO_HW_CFG_RGMII_ENA_SET(BIT(1)) |
			 HSIO_HW_CFG_GMII_ENA_SET(BIT(6))),
};

struct serdes_ctrl {
	void __iomem		*regs;
	struct device		*dev;
	struct phy		*phys[SERDES_MAX];
	int			ref125;
};

struct serdes_macro {
	u8			idx;
	int			port;
	struct serdes_ctrl	*ctrl;
	int			speed;
	phy_interface_t		mode;
};

enum lan966x_sd6g40_mode {
	LAN966X_SD6G40_MODE_QSGMII,
	LAN966X_SD6G40_MODE_SGMII,
};

enum lan966x_sd6g40_ltx2rx {
	LAN966X_SD6G40_TX2RX_LOOP_NONE,

Annotation

Immediate include surface: `linux/err.h`, `linux/module.h`, `linux/of.h`, `linux/of_platform.h`, `linux/phy.h`, `linux/phy/phy.h`, `linux/platform_device.h`, `dt-bindings/phy/phy-lan966x-serdes.h`.
Detected declarations: `struct serdes_mux`, `struct serdes_ctrl`, `struct serdes_macro`, `struct lan966x_sd6g40_setup_args`, `struct lan966x_sd6g40_mode_args`, `struct lan966x_sd6g40_setup`, `enum lan966x_sd6g40_mode`, `enum lan966x_sd6g40_ltx2rx`, `function lan_rmw_`, `function lan966x_sd6g40_reg_cfg`.
Atlas domain: Driver Families / drivers/phy.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.