drivers/phy/microchip/sparx5_serdes.c

Source file repositories/reference/linux-study-clean/drivers/phy/microchip/sparx5_serdes.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/microchip/sparx5_serdes.c
Extension
.c
Size
86355 bytes
Lines
2743
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sparx5_serdes_io_resource {
	enum sparx5_serdes_target id;
	phys_addr_t offset;
};

struct sparx5_sd25g28_mode_preset {
	u8 bitwidth;
	u8 tx_pre_div;
	u8 fifo_ck_div;
	u8 pre_divsel;
	u8 vco_div_mode;
	u8 sel_div;
	u8 ck_bitwidth;
	u8 subrate;
	u8 com_txcal_en;
	u8 com_tx_reserve_msb;
	u8 com_tx_reserve_lsb;
	u8 cfg_itx_ipcml_base;
	u8 tx_reserve_lsb;
	u8 tx_reserve_msb;
	u8 bw;
	u8 rxterm;
	u8 dfe_tap;
	u8 dfe_enable;
	bool txmargin;
	u8 cfg_ctle_rstn;
	u8 r_dfe_rstn;
	u8 cfg_pi_bw_3_0;
	u8 tx_tap_dly;
	u8 tx_tap_adv;
};

struct sparx5_sd25g28_media_preset {
	u8 cfg_eq_c_force_3_0;
	u8 cfg_vga_ctrl_byp_4_0;
	u8 cfg_eq_r_force_3_0;
	u8 cfg_en_adv;
	u8 cfg_en_main;
	u8 cfg_en_dly;
	u8 cfg_tap_adv_3_0;
	u8 cfg_tap_main;
	u8 cfg_tap_dly_4_0;
	u8 cfg_alos_thr_2_0;
};

struct sparx5_sd25g28_args {
	u8 if_width; /* UDL if-width: 10/16/20/32/64 */
	bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
	enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
	bool no_pwrcycle:1; /* Omit initial power-cycle */
	bool txinvert:1; /* Enable inversion of output data */
	bool rxinvert:1; /* Enable inversion of input data */
	u16 txswing; /* Set output level */
	u8 rate; /* Rate of network interface */
	u8 pi_bw_gen1;
	u8 duty_cycle; /* Set output level to  half/full */
	bool mute:1; /* Mute Output Buffer */
	bool reg_rst:1;
	u8 com_pll_reserve;
};

struct sparx5_sd25g28_params {
	u8 reg_rst;
	u8 cfg_jc_byp;
	u8 cfg_common_reserve_7_0;
	u8 r_reg_manual;
	u8 r_d_width_ctrl_from_hwt;
	u8 r_d_width_ctrl_2_0;
	u8 r_txfifo_ck_div_pmad_2_0;
	u8 r_rxfifo_ck_div_pmad_2_0;
	u8 cfg_pll_lol_set;
	u8 cfg_vco_div_mode_1_0;
	u8 cfg_pre_divsel_1_0;
	u8 cfg_sel_div_3_0;
	u8 cfg_vco_start_code_3_0;
	u8 cfg_pma_tx_ck_bitwidth_2_0;
	u8 cfg_tx_prediv_1_0;
	u8 cfg_rxdiv_sel_2_0;
	u8 cfg_tx_subrate_2_0;
	u8 cfg_rx_subrate_2_0;
	u8 r_multi_lane_mode;
	u8 cfg_cdrck_en;
	u8 cfg_dfeck_en;
	u8 cfg_dfe_pd;
	u8 cfg_dfedmx_pd;
	u8 cfg_dfetap_en_5_1;
	u8 cfg_dmux_pd;
	u8 cfg_dmux_clk_pd;
	u8 cfg_erramp_pd;
	u8 cfg_pi_dfe_en;

Annotation

Implementation Notes