drivers/phy/microchip/sparx5_serdes_regs.h

Source file repositories/reference/linux-study-clean/drivers/phy/microchip/sparx5_serdes_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/phy/microchip/sparx5_serdes_regs.h
Extension
.h
Size
130654 bytes
Lines
3040
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SPARX5_SERDES_REGS_H_
#define _SPARX5_SERDES_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

enum sparx5_serdes_target {
	TARGET_SD10G_LANE = 200,
	TARGET_SD25G_LANE = 212,
	TARGET_SD6G_LANE = 233,
	TARGET_SD_CMU = 248,
	TARGET_SD_CMU_CFG = 262,
	TARGET_SD_LANE = 276,
	TARGET_SD_LANE_25G = 301,
	NUM_TARGETS = 332
};

enum sparx5_serdes_tsize_enum {
	TC_SD10G_LANE,
	TC_SD_CMU,
	TC_SD_CMU_CFG,
	TC_SD_LANE,
	TSIZE_LAST,
};

/* sparx5_serdes.c */
extern const unsigned int *tsize;

#define TSIZE(o) tsize[o]

#define __REG(...)    __VA_ARGS__

/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
#define SD10G_LANE_LANE_01(t)                                                  \
	__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0,  \
	      1, 4)

#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)

#define SD10G_LANE_LANE_01_CFG_RXDET_EN          BIT(4)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)

#define SD10G_LANE_LANE_01_CFG_RXDET_STR         BIT(5)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)

/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
#define SD10G_LANE_LANE_02(t)                                                  \
	__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0,  \
	      1, 4)

#define SD10G_LANE_LANE_02_CFG_EN_ADV            BIT(0)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)

#define SD10G_LANE_LANE_02_CFG_EN_MAIN           BIT(1)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)

#define SD10G_LANE_LANE_02_CFG_EN_DLY            BIT(2)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)

#define SD10G_LANE_LANE_02_CFG_EN_DLY2           BIT(3)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)

#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0       GENMASK(7, 4)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)

Annotation

Implementation Notes