drivers/phy/phy-airoha-pcie-regs.h

Source file repositories/reference/linux-study-clean/drivers/phy/phy-airoha-pcie-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/phy/phy-airoha-pcie-regs.h
Extension
.h
Size
17466 bytes
Lines
495
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2024 AIROHA Inc
 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
 */

#ifndef _PHY_AIROHA_PCIE_H
#define _PHY_AIROHA_PCIE_H

/* CSR_2L */
#define REG_CSR_2L_CMN				0x0000
#define CSR_2L_PXP_CMN_LANE_EN			BIT(0)
#define CSR_2L_PXP_CMN_TRIM_MASK		GENMASK(28, 24)

#define REG_CSR_2L_JCPLL_IB_EXT			0x0004
#define REG_CSR_2L_JCPLL_LPF_SHCK_EN		BIT(8)
#define CSR_2L_PXP_JCPLL_CHP_IBIAS		GENMASK(21, 16)
#define CSR_2L_PXP_JCPLL_CHP_IOFST		GENMASK(29, 24)

#define REG_CSR_2L_JCPLL_LPF_BR			0x0008
#define CSR_2L_PXP_JCPLL_LPF_BR			GENMASK(4, 0)
#define CSR_2L_PXP_JCPLL_LPF_BC			GENMASK(12, 8)
#define CSR_2L_PXP_JCPLL_LPF_BP			GENMASK(20, 16)
#define CSR_2L_PXP_JCPLL_LPF_BWR		GENMASK(28, 24)

#define REG_CSR_2L_JCPLL_LPF_BWC		0x000c
#define CSR_2L_PXP_JCPLL_LPF_BWC		GENMASK(4, 0)
#define CSR_2L_PXP_JCPLL_KBAND_CODE		GENMASK(23, 16)
#define CSR_2L_PXP_JCPLL_KBAND_DIV		GENMASK(26, 24)

#define REG_CSR_2L_JCPLL_KBAND_KFC		0x0010
#define CSR_2L_PXP_JCPLL_KBAND_KFC		GENMASK(1, 0)
#define CSR_2L_PXP_JCPLL_KBAND_KF		GENMASK(9, 8)
#define CSR_2L_PXP_JCPLL_KBAND_KS		GENMASK(17, 16)
#define CSR_2L_PXP_JCPLL_POSTDIV_EN		BIT(24)

#define REG_CSR_2L_JCPLL_MMD_PREDIV_MODE	0x0014
#define CSR_2L_PXP_JCPLL_MMD_PREDIV_MODE	GENMASK(1, 0)
#define CSR_2L_PXP_JCPLL_POSTDIV_D2		BIT(16)
#define CSR_2L_PXP_JCPLL_POSTDIV_D5		BIT(24)

#define CSR_2L_PXP_JCPLL_MONCK			0x0018
#define CSR_2L_PXP_JCPLL_REFIN_DIV		GENMASK(25, 24)

#define REG_CSR_2L_JCPLL_RST_DLY		0x001c
#define CSR_2L_PXP_JCPLL_RST_DLY		GENMASK(2, 0)
#define CSR_2L_PXP_JCPLL_RST			BIT(8)
#define CSR_2L_PXP_JCPLL_SDM_DI_EN		BIT(16)
#define CSR_2L_PXP_JCPLL_SDM_DI_LS		GENMASK(25, 24)

#define REG_CSR_2L_JCPLL_SDM_IFM		0x0020
#define CSR_2L_PXP_JCPLL_SDM_IFM		BIT(0)

#define REG_CSR_2L_JCPLL_SDM_HREN		0x0024
#define CSR_2L_PXP_JCPLL_SDM_HREN		BIT(0)
#define CSR_2L_PXP_JCPLL_TCL_AMP_EN		BIT(8)
#define CSR_2L_PXP_JCPLL_TCL_AMP_GAIN		GENMASK(18, 16)
#define CSR_2L_PXP_JCPLL_TCL_AMP_VREF		GENMASK(28, 24)

#define REG_CSR_2L_JCPLL_TCL_CMP		0x0028
#define CSR_2L_PXP_JCPLL_TCL_LPF_EN		BIT(16)
#define CSR_2L_PXP_JCPLL_TCL_LPF_BW		GENMASK(26, 24)

#define REG_CSR_2L_JCPLL_VCODIV			0x002c
#define CSR_2L_PXP_JCPLL_VCO_CFIX		GENMASK(9, 8)
#define CSR_2L_PXP_JCPLL_VCO_HALFLSB_EN		BIT(16)
#define CSR_2L_PXP_JCPLL_VCO_SCAPWR		GENMASK(26, 24)

#define REG_CSR_2L_JCPLL_VCO_TCLVAR		0x0030
#define CSR_2L_PXP_JCPLL_VCO_TCLVAR		GENMASK(2, 0)

#define REG_CSR_2L_JCPLL_SSC				0x0038
#define CSR_2L_PXP_JCPLL_SSC_EN			BIT(0)
#define CSR_2L_PXP_JCPLL_SSC_PHASE_INI		BIT(8)
#define CSR_2L_PXP_JCPLL_SSC_TRI_EN		BIT(16)

#define REG_CSR_2L_JCPLL_SSC_DELTA1		0x003c
#define CSR_2L_PXP_JCPLL_SSC_DELTA1		GENMASK(15, 0)
#define CSR_2L_PXP_JCPLL_SSC_DELTA		GENMASK(31, 16)

#define REG_CSR_2L_JCPLL_SSC_PERIOD		0x0040
#define CSR_2L_PXP_JCPLL_SSC_PERIOD		GENMASK(15, 0)

#define REG_CSR_2L_JCPLL_TCL_VTP_EN		0x004c
#define CSR_2L_PXP_JCPLL_SPARE_LOW		GENMASK(31, 24)

#define REG_CSR_2L_JCPLL_TCL_KBAND_VREF		0x0050
#define CSR_2L_PXP_JCPLL_TCL_KBAND_VREF		GENMASK(4, 0)
#define CSR_2L_PXP_JCPLL_VCO_KBAND_MEAS_EN	BIT(24)

Annotation

Implementation Notes