drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
Extension
.c
Size
8547 bytes
Lines
327
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct m31_phy_tbl_entry {
	u32 off;
	u32 mask;
	u32 val;
};

struct m31_eusb2_priv_data {
	const struct m31_phy_tbl_entry	*setup_seq;
	unsigned int			setup_seq_nregs;
	const struct m31_phy_tbl_entry	*override_seq;
	unsigned int			override_seq_nregs;
	const struct m31_phy_tbl_entry	*reset_seq;
	unsigned int			reset_seq_nregs;
	unsigned int			fsel;
};

static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
};

static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = {
	M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0),
};

static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = {
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0),
	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0),
};

static const struct regulator_bulk_data m31_eusb_phy_vregs[] = {
	{ .supply = "vdd" },
	{ .supply = "vdda12" },
};

#define M31_EUSB_NUM_VREGS		ARRAY_SIZE(m31_eusb_phy_vregs)

struct m31eusb2_phy {
	struct phy			 *phy;
	void __iomem			 *base;
	const struct m31_eusb2_priv_data *data;
	enum phy_mode			 mode;

	struct regulator_bulk_data	 *vregs;
	struct clk			 *clk;
	struct reset_control		 *reset;

	struct phy			 *repeater;
};

static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset,
				       const u32 mask, u32 val)
{
	u32 write_val;
	u32 tmp;

	tmp = readl(base + offset);
	tmp &= ~mask;
	write_val = tmp | val;

	writel(write_val, base + offset);

	tmp = readl(base + offset);
	tmp &= mask;

	if (tmp != val) {
		pr_err("write: %x to offset: %x FAILED\n", val, offset);
		return -EINVAL;
	}

	return 0;
}

static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy,
				       const struct m31_phy_tbl_entry *tbl,
				       int num)
{
	int i;

Annotation

Implementation Notes