drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h

File Facts

System

Linux kernel

Corpus path

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h

Extension

.h

Size

660 bytes

Lines

21

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_

#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1			0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME		0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME		0x0f4
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5		0x108

#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x024
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x028

#endif

Annotation

• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.