drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
Extension
.h
Size
976 bytes
Lines
27
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_

/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2		0x00c
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5	0x084
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1			0x0a0
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST		0x0e0
#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME		0x0f0
#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME		0x0f4
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2		0x0fc
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5		0x108
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN			0x15c
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3	0x184

#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2		0x024
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2		0x028

#endif

Annotation

Implementation Notes