drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h

File Facts

System

Linux kernel

Corpus path

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h

Extension

.h

Size

1322 bytes

Lines

33

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_

/* Only for QMP V5 PHY - PCS_PCIE registers */
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2		0x0c
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4		0x14
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE		0x20
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L	0x44
#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H	0x48
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L	0x4c
#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H	0x50
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1		0x54
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1		0x5c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2		0x60
#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4		0x68
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2		0x7c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4		0x84
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5		0x88
#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6		0x8c
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS		0x94
#define QPHY_V5_PCS_PCIE_EQ_CONFIG1			0xa4
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2			0xa8
#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE			0xc0
#define QPHY_V5_PCS_PCIE_PRESET_P10_POST		0xe4

#endif

Annotation

• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.