drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
Extension
.h
Size
967 bytes
Lines
26
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_

/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2		0x00c
#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG		0x018
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE	0x01c
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS		0x090
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1			0x0a0
#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME		0x0f0
#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME		0x0f4
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5			0x108
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN			0x15c
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1	0x17c
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3	0x184
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5	0x18c
#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5		0x1ac
#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5		0x1c0

#endif

Annotation

Implementation Notes