drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h- Extension
.h- Size
- 580 bytes
- Lines
- 21
- Domain
- Driver Families
- Bucket
- drivers/phy
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef QCOM_PHY_QMP_PCS_SGMII_H_
#define QCOM_PHY_QMP_PCS_SGMII_H_
#define QPHY_PCS_PHY_START 0x000
#define QPHY_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_PCS_SW_RESET 0x008
#define QPHY_PCS_LINE_RESET_TIME 0x00c
#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
#define QPHY_PCS_PCS_READY_STATUS 0x094
#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
#define QPHY_PCS_SGMII_MISC_CTRL8 0x118
#endifAnnotation
- Atlas domain: Driver Families / drivers/phy.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.