drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h

File Facts

System

Linux kernel

Corpus path

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h

Extension

.h

Size

727 bytes

Lines

22

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_
#define QCOM_PHY_QMP_PCS_UFS_V3_H_

#define QPHY_V3_PCS_UFS_PHY_START			0x000
#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL		0x004
#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x02c
#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x034
#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL		0x134
#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME		0x138
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1			0x13c
#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2			0x140
#define QPHY_V3_PCS_UFS_READY_STATUS			0x160
#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1		0x1bc
#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1		0x1c4

#endif

Annotation

• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.