drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h

File Facts

System: Linux kernel
Corpus path: drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
Extension: .h
Size: 6355 bytes
Lines: 146
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_PCS_V3_H_
#define QCOM_PHY_QMP_PCS_V3_H_

/* Only for QMP V3 PHY - PCS registers */
#define QPHY_V3_PCS_SW_RESET				0x000
#define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
#define QPHY_V3_PCS_START_CONTROL			0x008
#define QPHY_V3_PCS_TXMGN_V0				0x00c
#define QPHY_V3_PCS_TXMGN_V1				0x010
#define QPHY_V3_PCS_TXMGN_V2				0x014
#define QPHY_V3_PCS_TXMGN_V3				0x018
#define QPHY_V3_PCS_TXMGN_V4				0x01c
#define QPHY_V3_PCS_TXMGN_LS				0x020
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0			0x024
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0			0x028
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1			0x02c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1			0x030
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2			0x034
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2			0x038
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3			0x03c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3			0x040
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4			0x044
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4			0x048
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS			0x04c
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS			0x050
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE		0x054
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL			0x058
#define QPHY_V3_PCS_RATE_SLEW_CNTRL			0x05c
#define QPHY_V3_PCS_POWER_STATE_CONFIG1			0x060
#define QPHY_V3_PCS_POWER_STATE_CONFIG2			0x064
#define QPHY_V3_PCS_POWER_STATE_CONFIG3			0x068
#define QPHY_V3_PCS_POWER_STATE_CONFIG4			0x06c
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L		0x070
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H		0x074
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L			0x078
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H			0x07c
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1			0x080
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2			0x084
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3			0x088
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME			0x08c
#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME		0x090
#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L		0x094
#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H		0x098
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK		0x09c
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8
#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL		0x0ac
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK		0x0b0
#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START		0x0b4
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME		0x0b8
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME		0x0bc
#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH		0x0c0
#define QPHY_V3_PCS_FLL_CNTRL1				0x0c4
#define QPHY_V3_PCS_FLL_CNTRL2				0x0c8
#define QPHY_V3_PCS_FLL_CNT_VAL_L			0x0cc
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL			0x0d0
#define QPHY_V3_PCS_FLL_MAN_CODE			0x0d4
#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL		0x0d8
#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR		0x0dc
#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD		0x0e0
#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY			0x0e4
#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL			0x0e8
#define QPHY_V3_PCS_INSIG_SW_CTRL1			0x0ec
#define QPHY_V3_PCS_INSIG_SW_CTRL2			0x0f0
#define QPHY_V3_PCS_INSIG_SW_CTRL3			0x0f4
#define QPHY_V3_PCS_INSIG_MX_CTRL1			0x0f8
#define QPHY_V3_PCS_INSIG_MX_CTRL2			0x0fc
#define QPHY_V3_PCS_INSIG_MX_CTRL3			0x100
#define QPHY_V3_PCS_OUTSIG_SW_CTRL1			0x104
#define QPHY_V3_PCS_OUTSIG_MX_CTRL1			0x108
#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL		0x10c
#define QPHY_V3_PCS_TEST_CONTROL			0x110
#define QPHY_V3_PCS_TEST_CONTROL2			0x114
#define QPHY_V3_PCS_TEST_CONTROL3			0x118
#define QPHY_V3_PCS_TEST_CONTROL4			0x11c
#define QPHY_V3_PCS_TEST_CONTROL5			0x120
#define QPHY_V3_PCS_TEST_CONTROL6			0x124
#define QPHY_V3_PCS_TEST_CONTROL7			0x128
#define QPHY_V3_PCS_COM_RESET_CONTROL			0x12c
#define QPHY_V3_PCS_BIST_CTRL				0x130
#define QPHY_V3_PCS_PRBS_POLY0				0x134
#define QPHY_V3_PCS_PRBS_POLY1				0x138
#define QPHY_V3_PCS_PRBS_SEED0				0x13c
#define QPHY_V3_PCS_PRBS_SEED1				0x140
#define QPHY_V3_PCS_FIXED_PAT_CTRL			0x144
#define QPHY_V3_PCS_FIXED_PAT0				0x148
#define QPHY_V3_PCS_FIXED_PAT1				0x14c
#define QPHY_V3_PCS_FIXED_PAT2				0x150
#define QPHY_V3_PCS_FIXED_PAT3				0x154

Annotation

Atlas domain: Driver Families / drivers/phy.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.