drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h

File Facts

System: Linux kernel
Corpus path: drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h
Extension: .h
Size: 32390 bytes
Lines: 640
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_QSERDES_V8_LALBH_
#define QCOM_PHY_QMP_QSERDES_V8_LALBH_

#define QSERDES_V8_LALB_BIST_MODE_LANENO	0x0
#define QSERDES_V8_LALB_BIST_INVERT	0x4
#define QSERDES_V8_LALB_PERL_LENGTH1	0x8
#define QSERDES_V8_LALB_PERL_LENGTH2	0xc
#define QSERDES_V8_LALB_BIST_PATTERN1	0x10
#define QSERDES_V8_LALB_BIST_PATTERN2	0x14
#define QSERDES_V8_LALB_BIST_PATTERN3	0x18
#define QSERDES_V8_LALB_BIST_PATTERN4	0x1c
#define QSERDES_V8_LALB_BIST_PATTERN5	0x20
#define QSERDES_V8_LALB_BIST_PATTERN6	0x24
#define QSERDES_V8_LALB_BIST_PATTERN7	0x28
#define QSERDES_V8_LALB_BIST_PATTERN8	0x2c
#define QSERDES_V8_LALB_PRBS_SEED1	0x30
#define QSERDES_V8_LALB_PRBS_SEED2	0x34
#define QSERDES_V8_LALB_PRBS_SEED3	0x38
#define QSERDES_V8_LALB_PRBS_SEED4	0x3c
#define QSERDES_V8_LALB_PRBS_SEED5	0x40
#define QSERDES_V8_LALB_PRBS_SEED6	0x44
#define QSERDES_V8_LALB_PRBS_SEED7	0x48
#define QSERDES_V8_LALB_SW_RESET_PWRDNB	0x4c
#define QSERDES_V8_LALB_RESET_GEN	0x50
#define QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL	0x54
#define QSERDES_V8_LALB_CDR_EN_RXEQ_RESET	0x58
#define QSERDES_V8_LALB_CLKBUF_ENABLE	0x5c
#define QSERDES_V8_LALB_TX0_EMP_POST1_LVL	0x60
#define QSERDES_V8_LALB_TX1_EMP_POST1_LVL	0x64
#define QSERDES_V8_LALB_TX0_IDLE_CTRL	0x68
#define QSERDES_V8_LALB_TX1_IDLE_CTRL	0x6c
#define QSERDES_V8_LALB_TX0_DRV_LVL	0x70
#define QSERDES_V8_LALB_TX0_DRV_LVL_OFFSET	0x74
#define QSERDES_V8_LALB_TX1_DRV_LVL	0x78
#define QSERDES_V8_LALB_TX1_DRV_LVL_OFFSET	0x7c
#define QSERDES_V8_LALB_TRAN_DRVR_EMP_EN	0x80
#define QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL	0x84
#define QSERDES_V8_LALB_TX0_PRE1_EMPH	0x88
#define QSERDES_V8_LALB_TX1_PRE1_EMPH	0x8c
#define QSERDES_V8_LALB_TX0_PRE2_EMPH	0x90
#define QSERDES_V8_LALB_TX1_PRE2_EMPH	0x94
#define QSERDES_V8_LALB_STALL_LDO_BOOST_EN	0x98
#define QSERDES_V8_LALB_PRE_EMPH_EN_CTRL	0x9c
#define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1	0xa0
#define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2	0xa4
#define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3	0xa8
#define QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4	0xac
#define QSERDES_V8_LALB_TRANSMITTER_EN_CTRL	0xb0
#define QSERDES_V8_LALB_HIGHZ_DRVR_EN	0xb4
#define QSERDES_V8_LALB_TX_MISC_CTRL1	0xb8
#define QSERDES_V8_LALB_LPB_EN_CTRL1	0xbc
#define QSERDES_V8_LALB_LBP_EN_CTRL2	0xc0
#define QSERDES_V8_LALB_TX0_SERDES_BYP_CTRL	0xc4
#define QSERDES_V8_LALB_TX1_SERDES_BYP_CTRL	0xc8
#define QSERDES_V8_LALB_LANE_MODE_1	0xcc
#define QSERDES_V8_LALB_LANE_MODE_2	0xd0
#define QSERDES_V8_LALB_LANE_MODE_3	0xd4
#define QSERDES_V8_LALB_LANE_MODE_4	0xd8
#define QSERDES_V8_LALB_ATB_SEL1	0xdc
#define QSERDES_V8_LALB_ATB_SEL2	0xe0
#define QSERDES_V8_LALB_TX0_RES_CODE_LANE	0xe4
#define QSERDES_V8_LALB_TX0_RESTRIM_ICAL_OVRD	0xe8
#define QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL	0xec
#define QSERDES_V8_LALB_TX0_RESTRIM_INIT_CODE	0xf0
#define QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET	0xf4
#define QSERDES_V8_LALB_TX1_RES_CODE_LANE	0xf8
#define QSERDES_V8_LALB_TX1_RESTRIM_ICAL_OVRD	0xfc
#define QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL	0x100
#define QSERDES_V8_LALB_TX1_RESTRIM_INIT_CODE	0x104
#define QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET	0x108
#define QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL	0x10c
#define QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL	0x110
#define QSERDES_V8_LALB_VMODE_CTRL1	0x114
#define QSERDES_V8_LALB_SLEW_CNTL_RATE01	0x118
#define QSERDES_V8_LALB_SLEW_CNTL_RATE23	0x11c
#define QSERDES_V8_LALB_SLEW_CNTL_RATE4	0x120
#define QSERDES_V8_LALB_ANA_INTERFACE_SELECT1	0x124
#define QSERDES_V8_LALB_ANA_INTERFACE_SELECT2	0x128
#define QSERDES_V8_LALB_ANA_INTERFACE_SELECT3	0x12c
#define QSERDES_V8_LALB_PCS_INTERFACE_SELECT1	0x130
#define QSERDES_V8_LALB_PCS_INTERFACE_SELECT2	0x134
#define QSERDES_V8_LALB_LDO_TIMER_CTRL	0x138
#define QSERDES_V8_LALB_AC_JTAG_ENABLE	0x13c
#define QSERDES_V8_LALB_AC_JTAG_INITP	0x140
#define QSERDES_V8_LALB_AC_JTAG_INITN	0x144
#define QSERDES_V8_LALB_AC_JTAG_LVL	0x148
#define QSERDES_V8_LALB_AC_JTAG_MODE	0x14c
#define QSERDES_V8_LALB_AC_JTAG_RESET	0x150
#define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0	0x154
#define QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1	0x158

Annotation

Atlas domain: Driver Families / drivers/phy.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.