drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h
Extension
.h
Size
8726 bytes
Lines
206
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_H_

/* Only for QMP V2 PHY - TX registers */
#define QSERDES_TX_BIST_MODE_LANENO			0x000
#define QSERDES_TX_BIST_INVERT				0x004
#define QSERDES_TX_CLKBUF_ENABLE			0x008
#define QSERDES_TX_CMN_CONTROL_ONE			0x00c
#define QSERDES_TX_CMN_CONTROL_TWO			0x010
#define QSERDES_TX_CMN_CONTROL_THREE			0x014
#define QSERDES_TX_TX_EMP_POST1_LVL			0x018
#define QSERDES_TX_TX_POST2_EMPH			0x01c
#define QSERDES_TX_TX_BOOST_LVL_UP_DN			0x020
#define QSERDES_TX_HP_PD_ENABLES			0x024
#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP		0x028
#define QSERDES_TX_TX_DRV_LVL				0x02c
#define QSERDES_TX_TX_DRV_LVL_OFFSET			0x030
#define QSERDES_TX_RESET_TSYNC_EN			0x034
#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN		0x038
#define QSERDES_TX_TX_BAND				0x03c
#define QSERDES_TX_SLEW_CNTL				0x040
#define QSERDES_TX_INTERFACE_SELECT			0x044
#define QSERDES_TX_LPB_EN				0x048
#define QSERDES_TX_RES_CODE_LANE_TX			0x04c
#define QSERDES_TX_RES_CODE_LANE_RX			0x050
#define QSERDES_TX_RES_CODE_LANE_OFFSET			0x054
#define QSERDES_TX_PERL_LENGTH1				0x058
#define QSERDES_TX_PERL_LENGTH2				0x05c
#define QSERDES_TX_SERDES_BYP_EN_OUT			0x060
#define QSERDES_TX_DEBUG_BUS_SEL			0x064
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x068
#define QSERDES_TX_TX_POL_INV				0x06c
#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN		0x070
#define QSERDES_TX_BIST_PATTERN1			0x074
#define QSERDES_TX_BIST_PATTERN2			0x078
#define QSERDES_TX_BIST_PATTERN3			0x07c
#define QSERDES_TX_BIST_PATTERN4			0x080
#define QSERDES_TX_BIST_PATTERN5			0x084
#define QSERDES_TX_BIST_PATTERN6			0x088
#define QSERDES_TX_BIST_PATTERN7			0x08c
#define QSERDES_TX_BIST_PATTERN8			0x090
#define QSERDES_TX_LANE_MODE				0x094
#define QSERDES_TX_IDAC_CAL_LANE_MODE			0x098
#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION	0x09c
#define QSERDES_TX_ATB_SEL1				0x0a0
#define QSERDES_TX_ATB_SEL2				0x0a4
#define QSERDES_TX_RCV_DETECT_LVL			0x0a8
#define QSERDES_TX_RCV_DETECT_LVL_2			0x0ac
#define QSERDES_TX_PRBS_SEED1				0x0b0
#define QSERDES_TX_PRBS_SEED2				0x0b4
#define QSERDES_TX_PRBS_SEED3				0x0b8
#define QSERDES_TX_PRBS_SEED4				0x0bc
#define QSERDES_TX_RESET_GEN				0x0c0
#define QSERDES_TX_RESET_GEN_MUXES			0x0c4
#define QSERDES_TX_TRAN_DRVR_EMP_EN			0x0c8
#define QSERDES_TX_TX_INTERFACE_MODE			0x0cc
#define QSERDES_TX_PWM_CTRL				0x0d0
#define QSERDES_TX_PWM_ENCODED_OR_DATA			0x0d4
#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2		0x0d8
#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2		0x0dc
#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2		0x0e0
#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2		0x0e4
#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1		0x0e8
#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1		0x0ec
#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1		0x0f0
#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1		0x0f4
#define QSERDES_TX_VMODE_CTRL1				0x0f8
#define QSERDES_TX_VMODE_CTRL2				0x0fc
#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL		0x100
#define QSERDES_TX_BIST_STATUS				0x104
#define QSERDES_TX_BIST_ERROR_COUNT1			0x108
#define QSERDES_TX_BIST_ERROR_COUNT2			0x10c
#define QSERDES_TX_TX_ALOG_INTF_OBSV			0x110

/* Only for QMP V2 PHY - RX registers */
#define QSERDES_RX_UCDR_FO_GAIN_HALF			0x000
#define QSERDES_RX_UCDR_FO_GAIN_QUARTER			0x004
#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH			0x008
#define QSERDES_RX_UCDR_FO_GAIN				0x00c
#define QSERDES_RX_UCDR_SO_GAIN_HALF			0x010
#define QSERDES_RX_UCDR_SO_GAIN_QUARTER			0x014
#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH			0x018
#define QSERDES_RX_UCDR_SO_GAIN				0x01c
#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF		0x020
#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER		0x024
#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH		0x028
#define QSERDES_RX_UCDR_SVS_FO_GAIN			0x02c
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF		0x030
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER		0x034
#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH		0x038

Annotation

Implementation Notes