drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

File Facts

System

Linux kernel

Corpus path

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h

Extension

.h

Size

2299 bytes

Lines

53

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_

#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX			0x28
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX			0x2c
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX		0x30
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX		0x34
#define QSERDES_UFS_V6_TX_LANE_MODE_1				0x7c
#define QSERDES_UFS_V6_TX_FR_DCC_CTRL				0x108

#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2		0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4		0x10
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4		0x24
#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION			0x28
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4	0x54
#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1				0x58
#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0			0xc4
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2			0xd4
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4			0xdc
#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4			0xf0
#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS			0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL			0x178
#define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4			0x1ac
#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x1bc
#define QSERDES_UFS_V6_RX_INTERFACE_MODE			0x1e0
#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3			0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0			0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1			0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2			0x210
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3			0x214
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4			0x218
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6			0x220
#define QSERDES_UFS_V6_RX_MODE_RATE2_B3				0x238
#define QSERDES_UFS_V6_RX_MODE_RATE2_B6				0x244
#define QSERDES_UFS_V6_RX_MODE_RATE3_B3				0x25c
#define QSERDES_UFS_V6_RX_MODE_RATE3_B4				0x260
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5				0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8				0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B0				0x274
#define QSERDES_UFS_V6_RX_MODE_RATE4_B1				0x278
#define QSERDES_UFS_V6_RX_MODE_RATE4_B2				0x27c
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3				0x280
#define QSERDES_UFS_V6_RX_MODE_RATE4_B4				0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6				0x28c
#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL			0x2f8

#endif

Annotation

• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.