drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h

File Facts

System: Linux kernel
Corpus path: drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h
Extension: .h
Size: 10444 bytes
Lines: 234
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_

/* Only for QMP V4 PHY - TX registers */
#define QSERDES_V4_TX_BIST_MODE_LANENO			0x000
#define QSERDES_V4_TX_BIST_INVERT			0x004
#define QSERDES_V4_TX_CLKBUF_ENABLE			0x008
#define QSERDES_V4_TX_TX_EMP_POST1_LVL			0x00c
#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP		0x010
#define QSERDES_V4_TX_TX_DRV_LVL			0x014
#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET			0x018
#define QSERDES_V4_TX_RESET_TSYNC_EN			0x01c
#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN		0x020
#define QSERDES_V4_TX_TX_BAND				0x024
#define QSERDES_V4_TX_SLEW_CNTL				0x028
#define QSERDES_V4_TX_INTERFACE_SELECT			0x02c
#define QSERDES_V4_TX_LPB_EN				0x030
#define QSERDES_V4_TX_RES_CODE_LANE_TX			0x034
#define QSERDES_V4_TX_RES_CODE_LANE_RX			0x038
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX		0x03c
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX		0x040
#define QSERDES_V4_TX_PERL_LENGTH1			0x044
#define QSERDES_V4_TX_PERL_LENGTH2			0x048
#define QSERDES_V4_TX_SERDES_BYP_EN_OUT			0x04c
#define QSERDES_V4_TX_DEBUG_BUS_SEL			0x050
#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN		0x054
#define QSERDES_V4_TX_HIGHZ_DRVR_EN			0x058
#define QSERDES_V4_TX_TX_POL_INV			0x05c
#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN	0x060
#define QSERDES_V4_TX_BIST_PATTERN1			0x064
#define QSERDES_V4_TX_BIST_PATTERN2			0x068
#define QSERDES_V4_TX_BIST_PATTERN3			0x06c
#define QSERDES_V4_TX_BIST_PATTERN4			0x070
#define QSERDES_V4_TX_BIST_PATTERN5			0x074
#define QSERDES_V4_TX_BIST_PATTERN6			0x078
#define QSERDES_V4_TX_BIST_PATTERN7			0x07c
#define QSERDES_V4_TX_BIST_PATTERN8			0x080
#define QSERDES_V4_TX_LANE_MODE_1			0x084
#define QSERDES_V4_TX_LANE_MODE_2			0x088
#define QSERDES_V4_TX_LANE_MODE_3			0x08c
#define QSERDES_V4_TX_ATB_SEL1				0x090
#define QSERDES_V4_TX_ATB_SEL2				0x094
#define QSERDES_V4_TX_RCV_DETECT_LVL			0x098
#define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x09c
#define QSERDES_V4_TX_PRBS_SEED1			0x0a0
#define QSERDES_V4_TX_PRBS_SEED2			0x0a4
#define QSERDES_V4_TX_PRBS_SEED3			0x0a8
#define QSERDES_V4_TX_PRBS_SEED4			0x0ac
#define QSERDES_V4_TX_RESET_GEN				0x0b0
#define QSERDES_V4_TX_RESET_GEN_MUXES			0x0b4
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0x0b8
#define QSERDES_V4_TX_TX_INTERFACE_MODE			0x0bc
#define QSERDES_V4_TX_PWM_CTRL				0x0c0
#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA		0x0c4
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2		0x0c8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2		0x0cc
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2		0x0d0
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2		0x0d4
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0x0d8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0x0dc
#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0x0e0
#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0x0e4
#define QSERDES_V4_TX_VMODE_CTRL1			0x0e8
#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1		0x0ec
#define QSERDES_V4_TX_BIST_STATUS			0x0f0
#define QSERDES_V4_TX_BIST_ERROR_COUNT1			0x0f4
#define QSERDES_V4_TX_BIST_ERROR_COUNT2			0x0f8
#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1		0x0fc
#define QSERDES_V4_TX_LANE_DIG_CONFIG			0x100
#define QSERDES_V4_TX_PI_QEC_CTRL			0x104
#define QSERDES_V4_TX_PRE_EMPH				0x108
#define QSERDES_V4_TX_SW_RESET				0x10c
#define QSERDES_V4_TX_DCC_OFFSET			0x110
#define QSERDES_V4_TX_DIG_BKUP_CTRL			0x114
#define QSERDES_V4_TX_DEBUG_BUS0			0x118
#define QSERDES_V4_TX_DEBUG_BUS1			0x11c
#define QSERDES_V4_TX_DEBUG_BUS2			0x120
#define QSERDES_V4_TX_DEBUG_BUS3			0x124
#define QSERDES_V4_TX_READ_EQCODE			0x128
#define QSERDES_V4_TX_READ_OFFSETCODE			0x12c
#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW		0x130
#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH		0x134
#define QSERDES_V4_TX_VGA_READ_CODE			0x138
#define QSERDES_V4_TX_VTH_READ_CODE			0x13c
#define QSERDES_V4_TX_DFE_TAP1_READ_CODE		0x140
#define QSERDES_V4_TX_DFE_TAP2_READ_CODE		0x144
#define QSERDES_V4_TX_IDAC_STATUS_I			0x148
#define QSERDES_V4_TX_IDAC_STATUS_IBAR			0x14c
#define QSERDES_V4_TX_IDAC_STATUS_Q			0x150
#define QSERDES_V4_TX_IDAC_STATUS_QBAR			0x154

Annotation

Atlas domain: Driver Families / drivers/phy.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.