drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h

File Facts

System: Linux kernel
Corpus path: drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h
Extension: .h
Size: 16750 bytes
Lines: 329
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_

/* Only for QMP V5 5NM PHY - TX registers */
#define QSERDES_V5_5NM_TX_BIST_MODE_LANENO			0x00
#define QSERDES_V5_5NM_TX_BIST_INVERT				0x04
#define QSERDES_V5_5NM_TX_CLKBUF_ENABLE				0x08
#define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL			0x0c
#define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP			0x10
#define QSERDES_V5_5NM_TX_TX_DRV_LVL				0x14
#define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET			0x18
#define QSERDES_V5_5NM_TX_RESET_TSYNC_EN			0x1c
#define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN		0x20
#define QSERDES_V5_5NM_TX_LPB_EN				0x24
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_TX			0x28
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_RX			0x2c
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX		0x30
#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX		0x34
#define QSERDES_V5_5NM_TX_PERL_LENGTH1				0x38
#define QSERDES_V5_5NM_TX_PERL_LENGTH2				0x3c
#define QSERDES_V5_5NM_TX_SERDES_BYP_EN_OUT			0x40
#define QSERDES_V5_5NM_TX_DEBUG_BUS_SEL				0x44
#define QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN			0x48
#define QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN				0x4c
#define QSERDES_V5_5NM_TX_TX_POL_INV				0x50
#define QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN		0x54
#define QSERDES_V5_5NM_TX_BIST_PATTERN1				0x58
#define QSERDES_V5_5NM_TX_BIST_PATTERN2				0x5c
#define QSERDES_V5_5NM_TX_BIST_PATTERN3				0x60
#define QSERDES_V5_5NM_TX_BIST_PATTERN4				0x64
#define QSERDES_V5_5NM_TX_BIST_PATTERN5				0x68
#define QSERDES_V5_5NM_TX_BIST_PATTERN6				0x6c
#define QSERDES_V5_5NM_TX_BIST_PATTERN7				0x70
#define QSERDES_V5_5NM_TX_BIST_PATTERN8				0x74
#define QSERDES_V5_5NM_TX_LANE_MODE_1				0x78
#define QSERDES_V5_5NM_TX_LANE_MODE_2				0x7c
#define QSERDES_V5_5NM_TX_LANE_MODE_3				0x80
#define QSERDES_V5_5NM_TX_ATB_SEL1				0x84
#define QSERDES_V5_5NM_TX_ATB_SEL2				0x88
#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL			0x8c
#define QSERDES_V5_5NM_TX_RCV_DETECT_LVL_2			0x90
#define QSERDES_V5_5NM_TX_PRBS_SEED1				0x94
#define QSERDES_V5_5NM_TX_PRBS_SEED2				0x98
#define QSERDES_V5_5NM_TX_PRBS_SEED3				0x9c
#define QSERDES_V5_5NM_TX_PRBS_SEED4				0xa0
#define QSERDES_V5_5NM_TX_RESET_GEN				0xa4
#define QSERDES_V5_5NM_TX_RESET_GEN_MUXES			0xa8
#define QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN			0xac
#define QSERDES_V5_5NM_TX_VMODE_CTRL1				0xb0
#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_CTRL_1			0xb4
#define QSERDES_V5_5NM_TX_BIST_STATUS				0xb8
#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT1			0xbc
#define QSERDES_V5_5NM_TX_BIST_ERROR_COUNT2			0xc0
#define QSERDES_V5_5NM_TX_ALOG_OBSV_BUS_STATUS_1		0xc4
#define QSERDES_V5_5NM_TX_LANE_DIG_CONFIG			0xc8
#define QSERDES_V5_5NM_TX_PI_QEC_CTRL				0xcc
#define QSERDES_V5_5NM_TX_PRE_EMPH				0xd0
#define QSERDES_V5_5NM_TX_SW_RESET				0xd4
#define QSERDES_V5_5NM_TX_TX_BAND				0xd8
#define QSERDES_V5_5NM_TX_SLEW_CNTL0				0xdc
#define QSERDES_V5_5NM_TX_SLEW_CNTL1				0xe0
#define QSERDES_V5_5NM_TX_INTERFACE_SELECT			0xe4
#define QSERDES_V5_5NM_TX_DIG_BKUP_CTRL				0xe8
#define QSERDES_V5_5NM_TX_DEBUG_BUS0				0xec
#define QSERDES_V5_5NM_TX_DEBUG_BUS1				0xf0
#define QSERDES_V5_5NM_TX_DEBUG_BUS2				0xf4
#define QSERDES_V5_5NM_TX_DEBUG_BUS3				0xf8
#define QSERDES_V5_5NM_TX_TX_BKUP_RO_BUS			0xfc

/* Only for QMP V5 5NM PHY - RX registers */
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE0		0x000
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE1		0x004
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE2		0x008
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_FO_GAIN_RATE3		0x00c
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE0		0x010
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE1		0x014
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE2		0x018
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_SO_GAIN_RATE3		0x01c
#define QSERDES_V5_5NM_RX_UCDR_SO_SATURATION			0x020
#define QSERDES_V5_5NM_RX_UCDR_FO_TO_SO_DELAY			0x024
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE0		0x028
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE0	0x02c
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE1		0x030
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE1	0x034
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE2		0x038
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE2	0x03c
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_LOW_RATE3		0x040
#define QSERDES_V5_5NM_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE3	0x044
#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL1				0x048
#define QSERDES_V5_5NM_RX_UCDR_PI_CTRL2				0x04c

Annotation

Atlas domain: Driver Families / drivers/phy.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.