drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
Extension
.c
Size
87737 bytes
Lines
2343
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qmp_ufs_offsets {
	u16 serdes;
	u16 pcs;
	u16 tx;
	u16 rx;
	u16 tx2;
	u16 rx2;
};

struct qmp_phy_cfg_tbls {
	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
	const struct qmp_phy_init_tbl *serdes;
	int serdes_num;
	const struct qmp_phy_init_tbl *tx;
	int tx_num;
	const struct qmp_phy_init_tbl *rx;
	int rx_num;
	const struct qmp_phy_init_tbl *pcs;
	int pcs_num;
	/* Maximum supported Gear of this tbls */
	u32 max_gear;
};

/* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg {
	int lanes;

	const struct qmp_ufs_offsets *offsets;
	/* Maximum supported Gear of this config */
	u32 max_supported_gear;

	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
	const struct qmp_phy_cfg_tbls tbls;
	/* Additional sequence for HS Series B */
	const struct qmp_phy_cfg_tbls tbls_hs_b;
	/* Additional sequence for different HS Gears */
	const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];

	/* regulators to be requested */
	const struct regulator_bulk_data *vreg_list;
	int num_vregs;

	/* array of registers with different offsets */
	const unsigned int *regs;

	/* true, if PCS block has no separate SW_RESET register */
	bool no_pcs_sw_reset;
};

struct qmp_ufs {
	struct device *dev;

	const struct qmp_phy_cfg *cfg;

	void __iomem *serdes;
	void __iomem *pcs;
	void __iomem *pcs_misc;
	void __iomem *tx;
	void __iomem *rx;
	void __iomem *tx2;
	void __iomem *rx2;

	struct clk_bulk_data *clks;
	int num_clks;
	struct regulator_bulk_data *vregs;
	struct reset_control *ufs_reset;

	struct phy *phy;
	u32 mode;
	u32 submode;
};

static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
{
	u32 reg;

	reg = readl(base + offset);
	reg |= val;
	writel(reg, base + offset);

	/* ensure that above write is through */
	readl(base + offset);
}

static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
{
	u32 reg;

	reg = readl(base + offset);
	reg &= ~val;

Annotation

Implementation Notes