drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
Extension
.c
Size
16361 bytes
Lines
644
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct override_param {
	s32	value;
	u8	reg_val;
};

struct override_param_map {
	const char *prop_name;
	const struct override_param *param_table;
	u8 table_size;
	u8 reg_offset;
	u8 param_mask;
};

struct phy_override_seq {
	bool	need_update;
	u8	offset;
	u8	value;
	u8	mask;
};

#define NUM_HSPHY_TUNING_PARAMS	(9)

/**
 * struct qcom_snps_hsphy - snps hs phy attributes
 *
 * @dev: device structure
 *
 * @phy: generic phy
 * @base: iomapped memory space for snps hs phy
 *
 * @num_clks: number of clocks
 * @clks: array of clocks
 * @phy_reset: phy reset control
 * @vregs: regulator supplies bulk data
 * @phy_initialized: if PHY has been initialized correctly
 * @mode: contains the current mode the PHY is in
 * @update_seq_cfg: tuning parameters for phy init
 */
struct qcom_snps_hsphy {
	struct device *dev;

	struct phy *phy;
	void __iomem *base;

	int num_clks;
	struct clk_bulk_data *clks;
	struct reset_control *phy_reset;
	struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];

	bool phy_initialized;
	enum phy_mode mode;
	struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
};

static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy)
{
	struct device *dev = hsphy->dev;

	hsphy->num_clks = 2;
	hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL);
	if (!hsphy->clks)
		return -ENOMEM;

	/*
	 * TODO: Currently no device tree instantiation of the PHY is using the clock.
	 * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get().
	 */
	hsphy->clks[0].id = "cfg_ahb";
	hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb");
	if (IS_ERR(hsphy->clks[0].clk))
		return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk),
				     "failed to get cfg_ahb clk\n");

	hsphy->clks[1].id = "ref";
	hsphy->clks[1].clk = devm_clk_get(dev, "ref");
	if (IS_ERR(hsphy->clks[1].clk))
		return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk),
				     "failed to get ref clk\n");

	return 0;
}

static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
						u32 mask, u32 val)
{
	u32 reg;

	reg = readl_relaxed(base + offset);
	reg &= ~mask;
	reg |= val & mask;

Annotation

Implementation Notes