drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c

Source file repositories/reference/linux-study-clean/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
Extension
.c
Size
8287 bytes
Lines
332
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qcom_uniphy_pcie_regs {
	u32 offset;
	u32 val;
};

struct qcom_uniphy_pcie_data {
	int lane_offset; /* offset between the lane register bases */
	u32 phy_type;
	const struct qcom_uniphy_pcie_regs *init_seq;
	u32 init_seq_num;
	u32 pipe_clk_rate;
};

struct qcom_uniphy_pcie {
	struct phy phy;
	struct device *dev;
	const struct qcom_uniphy_pcie_data *data;
	struct clk_bulk_data *clks;
	int num_clks;
	struct reset_control *resets;
	void __iomem *base;
	int lanes;
};

#define phy_to_dw_phy(x)	container_of((x), struct qca_uni_pcie_phy, phy)

static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
	{
		.offset = SSCG_CTRL_REG_4,
		.val = 0x1cb9,
	}, {
		.offset = SSCG_CTRL_REG_5,
		.val = 0x023a,
	}, {
		.offset = SSCG_CTRL_REG_3,
		.val = 0xd360,
	}, {
		.offset = SSCG_CTRL_REG_1,
		.val = 0x1,
	}, {
		.offset = SSCG_CTRL_REG_2,
		.val = 0xeb,
	}, {
		.offset = CDR_CTRL_REG_4,
		.val = 0x3f9,
	}, {
		.offset = CDR_CTRL_REG_5,
		.val = 0x1c9,
	}, {
		.offset = CDR_CTRL_REG_2,
		.val = 0x419,
	}, {
		.offset = CDR_CTRL_REG_1,
		.val = 0x200,
	}, {
		.offset = PCS_INTERNAL_CONTROL_2,
		.val = 0xf101,
	},
};

static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
	{
		.offset = PHY_CFG_PLLCFG,
		.val = 0x30,
	}, {
		.offset = PHY_CFG_EIOS_DTCT_REG,
		.val = 0x53ef,
	}, {
		.offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
		.val = 0xcf,
	},
};

static const struct qcom_uniphy_pcie_data ipq5018_data = {
	.lane_offset	= 0x800,
	.phy_type	= PHY_TYPE_PCIE_GEN2,
	.init_seq	= ipq5018_regs,
	.init_seq_num	= ARRAY_SIZE(ipq5018_regs),
	.pipe_clk_rate	= 125 * MEGA,
};

static const struct qcom_uniphy_pcie_data ipq5332_data = {
	.lane_offset	= 0x800,
	.phy_type	= PHY_TYPE_PCIE_GEN3,
	.init_seq	= ipq5332_regs,
	.init_seq_num	= ARRAY_SIZE(ipq5332_regs),
	.pipe_clk_rate	= 250 * MEGA,
};

static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)

Annotation

Implementation Notes