drivers/phy/ralink/Kconfig

Source file repositories/reference/linux-study-clean/drivers/phy/ralink/Kconfig

File Facts

System: Linux kernel
Corpus path: drivers/phy/ralink/Kconfig
Extension: [no extension]
Size: 565 bytes
Lines: 22
Domain: Driver Families
Bucket: drivers/phy
Inferred role: Driver Families: build/configuration rule
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
#
# PHY drivers for Ralink platforms.
#
config PHY_MT7621_PCI
	tristate "MediaTek MT7621 PCI PHY Driver"
	depends on (RALINK && OF) || COMPILE_TEST
	select GENERIC_PHY
	select REGMAP_MMIO
	help
	  Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver,

config PHY_RALINK_USB
	tristate "Ralink USB PHY driver"
	depends on RALINK || COMPILE_TEST
	depends on HAS_IOMEM
	select GENERIC_PHY
	select MFD_SYSCON
	help
	  This option enables support for the Ralink USB PHY found inside
	  RT3352, MT7620, MT7628 and MT7688.

Annotation

Atlas domain: Driver Families / drivers/phy.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.