drivers/phy/renesas/phy-rzg3e-usb3.c

Source file repositories/reference/linux-study-clean/drivers/phy/renesas/phy-rzg3e-usb3.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/renesas/phy-rzg3e-usb3.c
Extension
.c
Size
7062 bytes
Lines
260
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rz_usb3 {
	void __iomem *base;
	struct reset_control *rstc;
	bool skip_reinit;
};

static void rzg3e_phy_usb2test_phy_init(void __iomem *base)
{
	u32 val;

	val = readl(base + USB3_TEST_UTMICTRL2);
	val |= USB3_TEST_UTMICTRL2_CTRL_MASK | USB3_TEST_UTMICTRL2_MODE_MASK;
	writel(val, base + USB3_TEST_UTMICTRL2);

	val = readl(base + USB3_TEST_PRMCTRL5_R);
	val &= ~USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK;
	val |= FIELD_PREP(USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK, 2);
	writel(val, base + USB3_TEST_PRMCTRL5_R);

	val = readl(base + USB3_TEST_PRMCTRL6_R);
	val &= ~USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK;
	val |= FIELD_PREP(USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK, 7);
	writel(val, base + USB3_TEST_PRMCTRL6_R);

	val = readl(base + USB3_TEST_RESET);
	val &= ~USB3_TEST_RESET_SIDDQ;
	val |= USB3_TEST_RESET_PORTRESET0_CTRL | USB3_TEST_RESET_PHY_RESET |
	       USB3_TEST_RESET_PORTRESET0;
	writel(val, base + USB3_TEST_RESET);
	fsleep(10);

	val &= ~(USB3_TEST_RESET_PHY_RESET | USB3_TEST_RESET_PORTRESET0);
	writel(val, base + USB3_TEST_RESET);
	fsleep(10);

	val = readl(base + USB3_TEST_UTMICTRL2);
	val &= ~USB3_TEST_UTMICTRL2_CTRL_MASK;
	writel(val, base + USB3_TEST_UTMICTRL2);

	writel(USB3_TEST_RESET_RELEASE_OVERRIDE, base + USB3_TEST_RESET);
}

static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
{
	int ret;
	u32 val;

	writel(USB3_TEST_CREGCTRL_PARA_SEL, base + USB3_TEST_CREGCTRL);
	writel(USB3_TEST_RSTCTRL_ASSERT, base + USB3_TEST_RSTCTRL);
	fsleep(20);

	writel(USB3_TEST_CLKCTRL_MPLLA_SSC_EN, base + USB3_TEST_CLKCTRL);
	writel(USB3_TEST_LANECONFIG0_DEFAULT, base + USB3_TEST_LANECONFIG0);
	writel(USB3_TEST_RSTCTRL_RELEASE_HARDRESET, base + USB3_TEST_RSTCTRL);

	ret = readl_poll_timeout_atomic(base + USB3_TEST_RAMCTRL, val,
					val & USB3_TEST_RAMCTRL_SRAM_INIT_DONE, 1, 10000);
	if (ret)
		return ret;

	writel(USB3_TEST_RSTCTRL_DEASSERT, base + USB3_TEST_RSTCTRL);
	writel(USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE, base + USB3_TEST_RAMCTRL);
	writel(USB3_TEST_RSTCTRL_RELEASE_OVERRIDE, base + USB3_TEST_RSTCTRL);

	return 0;
}

static int rzg3e_phy_usb3_init_helper(void __iomem *base)
{
	rzg3e_phy_usb2test_phy_init(base);

	return rzg3e_phy_usb3test_phy_init(base);
}

static int rzg3e_phy_usb3_init(struct phy *p)
{
	struct rz_usb3 *r = phy_get_drvdata(p);
	int ret = 0;

	if (!r->skip_reinit)
		ret = rzg3e_phy_usb3_init_helper(r->base);

	return ret;
}

static const struct phy_ops rzg3e_phy_usb3_ops = {
	.init = rzg3e_phy_usb3_init,
	.owner = THIS_MODULE,
};

Annotation

Implementation Notes