drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

File Facts

System

Linux kernel

Corpus path

drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c

Extension

.c

Size

80029 bytes

Lines

2565

Domain

Driver Families

Bucket

drivers/phy

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/bitfield.h
• linux/clk.h
• linux/clk-provider.h
• linux/delay.h
• linux/mfd/syscon.h
• linux/module.h
• linux/of.h
• linux/of_platform.h
• linux/phy/phy.h
• linux/platform_device.h
• linux/pm_runtime.h
• linux/rational.h
• linux/regmap.h
• linux/reset.h

Detected Declarations

• struct lcpll_config
• struct ropll_config
• struct tx_drv_ctrl
• struct rk_hdptx_phy_cfg
• struct rk_hdptx_hdmi_cfg
• struct rk_hdptx_phy
• enum dp_link_rate
• enum rk_hdptx_reset
• function rk_hdptx_phy_is_rw_reg
• function rk_hdptx_pre_power_up
• function rk_hdptx_post_enable_lane
• function rk_hdptx_post_enable_pll
• function rk_hdptx_phy_disable
• function rk_hdptx_phy_clk_pll_calc
• function rk_hdptx_frl_lcpll_cmn_config
• function rk_hdptx_frl_lcpll_ropll_cmn_config
• function rk_hdptx_tmds_ropll_cmn_config
• function rk_hdptx_pll_cmn_config
• function rk_hdptx_frl_lcpll_mode_config
• function rk_hdptx_tmds_ropll_mode_config
• function rk_hdptx_dp_reset
• function rk_hdptx_phy_consumer_get
• function rk_hdptx_phy_consumer_put
• function rk_hdptx_dp_pll_init
• function rk_hdptx_dp_aux_init
• function rk_hdptx_phy_power_on
• function rk_hdptx_phy_power_off
• function rk_hdptx_phy_verify_hdmi_config
• function rk_hdptx_phy_verify_dp_config
• function rk_hdptx_phy_set_rate
• function rk_hdptx_phy_set_lanes
• function rk_hdptx_phy_set_voltage
• function rk_hdptx_phy_set_voltages
• function rk_hdptx_phy_set_mode
• function rk_hdptx_phy_configure
• function rk_hdptx_phy_validate
• function rk_hdptx_phy_clk_prepare
• function rk_hdptx_phy_clk_unprepare
• function rk_hdptx_phy_clk_calc_rate_from_pll_cfg
• function rk_hdptx_phy_clk_recalc_rate
• function rk_hdptx_phy_clk_determine_rate
• function phy_configure
• function rk_hdptx_phy_clk_set_rate
• function rk_hdptx_phy_clk_register
• function rk_hdptx_phy_runtime_suspend
• function rk_hdptx_phy_runtime_resume
• function rk_hdptx_phy_probe

Annotated Snippet

struct lcpll_config {
	unsigned long long rate;
	u8 lcvco_mode_en;
	u8 pi_en;
	u8 clk_en_100m;
	u8 pms_mdiv;
	u8 pms_mdiv_afc;
	u8 pms_pdiv;
	u8 pms_refdiv;
	u8 pms_sdiv;
	u8 sdm_deno;
	u8 sdm_num_sign;
	u8 sdm_num;
	u8 sdc_n;
};

struct ropll_config {
	unsigned long long rate;
	u8 pms_mdiv;
	u8 pms_mdiv_afc;
	u8 pms_pdiv;
	u8 pms_refdiv;
	u8 pms_sdiv;
	u8 sdm_en;
	u8 sdm_deno;
	u8 sdm_num_sign;
	u8 sdm_num;
	u8 sdc_n;
	u8 sdc_num;
	u8 sdc_deno;
};

struct tx_drv_ctrl {
	u8 tx_drv_lvl_ctrl;
	u8 tx_drv_post_lvl_ctrl;
	u8 ana_tx_drv_idrv_idn_ctrl;
	u8 ana_tx_drv_idrv_iup_ctrl;
	u8 ana_tx_drv_accdrv_en;
	u8 ana_tx_drv_accdrv_ctrl;
	u8 tx_drv_pre_lvl_ctrl;
	u8 ana_tx_jeq_en;
	u8 tx_jeq_even_ctrl;
	u8 tx_jeq_odd_ctrl;
};

enum rk_hdptx_reset {
	RST_APB = 0,
	RST_INIT,
	RST_CMN,
	RST_LANE,
	RST_MAX
};

#define MAX_HDPTX_PHY_NUM	2

struct rk_hdptx_phy_cfg {
	unsigned int num_phys;
	unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
};

struct rk_hdptx_hdmi_cfg {
	enum phy_hdmi_mode mode;
	unsigned long long rate;
	unsigned int bpc;
};

struct rk_hdptx_phy {
	struct device *dev;
	struct regmap *regmap;
	struct regmap *grf;

	int phy_id;
	struct phy *phy;
	struct rk_hdptx_hdmi_cfg hdmi_cfg;
	struct clk_bulk_data *clks;
	int nr_clks;
	struct reset_control_bulk_data rsts[RST_MAX];

	/* clk provider */
	struct clk_hw hw;
	bool restrict_rate_change;

	atomic_t usage_count;

	/* used for dp mode */
	unsigned int link_rate;
	unsigned int lanes;
};

static const struct lcpll_config rk_hdptx_frl_lcpll_cfg[] = {

Annotation

• Immediate include surface: `linux/bitfield.h`, `linux/clk.h`, `linux/clk-provider.h`, `linux/delay.h`, `linux/mfd/syscon.h`, `linux/module.h`, `linux/of.h`, `linux/of_platform.h`.
• Detected declarations: `struct lcpll_config`, `struct ropll_config`, `struct tx_drv_ctrl`, `struct rk_hdptx_phy_cfg`, `struct rk_hdptx_hdmi_cfg`, `struct rk_hdptx_phy`, `enum dp_link_rate`, `enum rk_hdptx_reset`, `function rk_hdptx_phy_is_rw_reg`, `function rk_hdptx_pre_power_up`.
• Atlas domain: Driver Families / drivers/phy.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.