drivers/phy/samsung/phy-exynos4210-usb2.c

Source file repositories/reference/linux-study-clean/drivers/phy/samsung/phy-exynos4210-usb2.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/samsung/phy-exynos4210-usb2.c
Extension
.c
Size
7036 bytes
Lines
258
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 support
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 * Author: Kamil Debski <k.debski@samsung.com>
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include "phy-samsung-usb2.h"

/* Exynos USB PHY registers */

/* PHY power control */
#define EXYNOS_4210_UPHYPWR			0x0

#define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND	BIT(0)
#define EXYNOS_4210_UPHYPWR_PHY0_PWR		BIT(3)
#define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR	BIT(4)
#define EXYNOS_4210_UPHYPWR_PHY0_SLEEP		BIT(5)
#define EXYNOS_4210_UPHYPWR_PHY0	( \
	EXYNOS_4210_UPHYPWR_PHY0_SUSPEND | \
	EXYNOS_4210_UPHYPWR_PHY0_PWR | \
	EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR | \
	EXYNOS_4210_UPHYPWR_PHY0_SLEEP)

#define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND	BIT(6)
#define EXYNOS_4210_UPHYPWR_PHY1_PWR		BIT(7)
#define EXYNOS_4210_UPHYPWR_PHY1_SLEEP		BIT(8)
#define EXYNOS_4210_UPHYPWR_PHY1 ( \
	EXYNOS_4210_UPHYPWR_PHY1_SUSPEND | \
	EXYNOS_4210_UPHYPWR_PHY1_PWR | \
	EXYNOS_4210_UPHYPWR_PHY1_SLEEP)

#define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND	BIT(9)
#define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP		BIT(10)
#define EXYNOS_4210_UPHYPWR_HSIC0 ( \
	EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND | \
	EXYNOS_4210_UPHYPWR_HSIC0_SLEEP)

#define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND	BIT(11)
#define EXYNOS_4210_UPHYPWR_HSIC1_SLEEP		BIT(12)
#define EXYNOS_4210_UPHYPWR_HSIC1 ( \
	EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND | \
	EXYNOS_4210_UPHYPWR_HSIC1_SLEEP)

/* PHY clock control */
#define EXYNOS_4210_UPHYCLK			0x4

#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
#define EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET	0
#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)

#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
#define EXYNOS_4210_UPHYCLK_PHY0_COMMON_ON	BIT(4)
#define EXYNOS_4210_UPHYCLK_PHY1_COMMON_ON	BIT(7)

/* PHY reset control */
#define EXYNOS_4210_UPHYRST			0x8

#define EXYNOS_4210_URSTCON_PHY0		BIT(0)
#define EXYNOS_4210_URSTCON_OTG_HLINK		BIT(1)
#define EXYNOS_4210_URSTCON_OTG_PHYLINK		BIT(2)
#define EXYNOS_4210_URSTCON_PHY1_ALL		BIT(3)
#define EXYNOS_4210_URSTCON_PHY1_P0		BIT(4)
#define EXYNOS_4210_URSTCON_PHY1_P1P2		BIT(5)
#define EXYNOS_4210_URSTCON_HOST_LINK_ALL	BIT(6)
#define EXYNOS_4210_URSTCON_HOST_LINK_P0	BIT(7)
#define EXYNOS_4210_URSTCON_HOST_LINK_P1	BIT(8)
#define EXYNOS_4210_URSTCON_HOST_LINK_P2	BIT(9)

/* Isolation, configured in the power management unit */
#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET	0x704
#define EXYNOS_4210_USB_ISOL_DEVICE		BIT(0)
#define EXYNOS_4210_USB_ISOL_HOST_OFFSET	0x708
#define EXYNOS_4210_USB_ISOL_HOST		BIT(0)

/* USBYPHY1 Floating prevention */
#define EXYNOS_4210_UPHY1CON			0x34
#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION	0x1

/* Mode switching SUB Device <-> Host */
#define EXYNOS_4210_MODE_SWITCH_OFFSET		0x21c
#define EXYNOS_4210_MODE_SWITCH_MASK		1
#define EXYNOS_4210_MODE_SWITCH_DEVICE		0

Annotation

Implementation Notes