drivers/phy/samsung/phy-exynos5-usbdrd.c

Source file repositories/reference/linux-study-clean/drivers/phy/samsung/phy-exynos5-usbdrd.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/samsung/phy-exynos5-usbdrd.c
Extension
.c
Size
94294 bytes
Lines
3072
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct exynos5_usbdrd_phy_tuning {
	u32 off;
	u32 mask;
	u32 val;
	char region;
#define PTR_INVALID	0
#define PTR_PHY		1
#define PTR_PCS		2
#define PTR_PMA		3
};

enum exynos5_usbdrd_phy_tuning_state {
	PTS_UTMI_POSTINIT,
	PTS_PIPE3_PREINIT,
	PTS_PIPE3_INIT,
	PTS_PIPE3_POSTINIT,
	PTS_PIPE3_POSTLOCK,
	PTS_MAX,
};

enum exynos5_usbdrd_phy_id {
	EXYNOS5_DRDPHY_UTMI,
	EXYNOS5_DRDPHY_PIPE3,
	EXYNOS5_DRDPHYS_NUM,
};

struct phy_usb_instance;
struct exynos5_usbdrd_phy;

struct exynos5_usbdrd_phy_config {
	u32 id;
	void (*phy_isol)(struct phy_usb_instance *inst, bool isolate);
	void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
	unsigned int (*set_refclk)(struct phy_usb_instance *inst);
};

struct exynos5_usbdrd_phy_drvdata {
	const struct exynos5_usbdrd_phy_config *phy_cfg;
	const struct exynos5_usbdrd_phy_tuning **phy_tunes;
	const struct phy_ops *phy_ops;
	const char * const *clk_names;
	int n_clks;
	const char * const *core_clk_names;
	int n_core_clks;
	const char * const *regulator_names;
	int n_regulators;
	u32 pmu_offset_usbdrd0_phy;
	u32 pmu_offset_usbdrd0_phy_ss;
	u32 pmu_offset_usbdrd1_phy;
};

/**
 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
 * @dev: pointer to device instance of this platform device
 * @reg_phy: usb phy controller register memory base
 * @reg_pcs: usb phy physical coding sublayer register memory base
 * @reg_pma: usb phy physical media attachment register memory base
 * @clks: clocks for register access
 * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
 * @drv_data: pointer to SoC level driver data structure
 * @hs_phy: pointer to non-Samsung IP high-speed phy controller
 * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks
 * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
 *	    instances each with its 'phy' and 'phy_cfg'.
 * @extrefclk: frequency select settings when using 'separate
 *	       reference clocks' for SS and HS operations
 * @regulators: regulators for phy
 * @sw: TypeC orientation switch handle
 * @orientation: TypeC connector orientation - normal or flipped
 */
struct exynos5_usbdrd_phy {
	struct device *dev;
	void __iomem *reg_phy;
	void __iomem *reg_pcs;
	void __iomem *reg_pma;
	struct clk_bulk_data *clks;
	struct clk_bulk_data *core_clks;
	const struct exynos5_usbdrd_phy_drvdata *drv_data;
	struct phy *hs_phy;
	struct mutex phy_mutex;
	struct phy_usb_instance {
		struct phy *phy;
		u32 index;
		struct regmap *reg_pmu;
		u32 pmu_offset;
		const struct exynos5_usbdrd_phy_config *phy_cfg;
	} phys[EXYNOS5_DRDPHYS_NUM];
	u32 extrefclk;
	struct regulator_bulk_data *regulators;

Annotation

Implementation Notes