drivers/phy/samsung/phy-exynos5250-usb2.c

Source file repositories/reference/linux-study-clean/drivers/phy/samsung/phy-exynos5250-usb2.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/samsung/phy-exynos5250-usb2.c
Extension
.c
Size
13631 bytes
Lines
419
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 * Author: Kamil Debski <k.debski@samsung.com>
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include "phy-samsung-usb2.h"

/* Exynos USB PHY registers */
#define EXYNOS_5250_REFCLKSEL_CRYSTAL	0x0
#define EXYNOS_5250_REFCLKSEL_XO	0x1
#define EXYNOS_5250_REFCLKSEL_CLKCORE	0x2

#define EXYNOS_5250_FSEL_9MHZ6		0x0
#define EXYNOS_5250_FSEL_10MHZ		0x1
#define EXYNOS_5250_FSEL_12MHZ		0x2
#define EXYNOS_5250_FSEL_19MHZ2		0x3
#define EXYNOS_5250_FSEL_20MHZ		0x4
#define EXYNOS_5250_FSEL_24MHZ		0x5
#define EXYNOS_5250_FSEL_50MHZ		0x7

/* Normal host */
#define EXYNOS_5250_HOSTPHYCTRL0			0x0

#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL		BIT(31)
#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT	19
#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK	\
		(0x3 << EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT)
#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT		16
#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \
		(0x7 << EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT)
#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN		BIT(11)
#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE		BIT(10)
#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N		BIT(9)
#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK		(0x3 << 7)
#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL		(0x0 << 7)
#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0		(0x1 << 7)
#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST	(0x2 << 7)
#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ			BIT(6)
#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP		BIT(5)
#define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND		BIT(4)
#define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE		BIT(3)
#define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST		BIT(2)
#define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST		BIT(1)
#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRST		BIT(0)

/* HSIC0 & HSIC1 */
#define EXYNOS_5250_HSICPHYCTRL1			0x10
#define EXYNOS_5250_HSICPHYCTRL2			0x20

#define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_MASK		(0x3 << 23)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKSEL_DEFAULT	(0x2 << 23)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_MASK		(0x7f << 16)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_12		(0x24 << 16)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_15		(0x1c << 16)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_16		(0x1a << 16)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_19_2		(0x15 << 16)
#define EXYNOS_5250_HSICPHYCTRLX_REFCLKDIV_20		(0x14 << 16)
#define EXYNOS_5250_HSICPHYCTRLX_SIDDQ			BIT(6)
#define EXYNOS_5250_HSICPHYCTRLX_FORCESLEEP		BIT(5)
#define EXYNOS_5250_HSICPHYCTRLX_FORCESUSPEND		BIT(4)
#define EXYNOS_5250_HSICPHYCTRLX_WORDINTERFACE		BIT(3)
#define EXYNOS_5250_HSICPHYCTRLX_UTMISWRST		BIT(2)
#define EXYNOS_5250_HSICPHYCTRLX_PHYSWRST		BIT(0)

/* EHCI control */
#define EXYNOS_5250_HOSTEHCICTRL			0x30
#define EXYNOS_5250_HOSTEHCICTRL_ENAINCRXALIGN		BIT(29)
#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR4		BIT(28)
#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR8		BIT(27)
#define EXYNOS_5250_HOSTEHCICTRL_ENAINCR16		BIT(26)
#define EXYNOS_5250_HOSTEHCICTRL_AUTOPPDONOVRCUREN	BIT(25)
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT	19
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK	\
		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT	13
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_MASK	\
		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL1_SHIFT)
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL2_SHIFT	7
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_MASK	\
		(0x3f << EXYNOS_5250_HOSTEHCICTRL_FLADJVAL0_SHIFT)
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT	1
#define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_MASK \
		(0x1 << EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT)

Annotation

Implementation Notes