drivers/phy/samsung/phy-gs101-ufs.c

Source file repositories/reference/linux-study-clean/drivers/phy/samsung/phy-gs101-ufs.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/samsung/phy-gs101-ufs.c
Extension
.c
Size
7813 bytes
Lines
211
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * UFS PHY driver data for Google Tensor gs101 SoC
 *
 * Copyright (C) 2024 Linaro Ltd
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */

#include "phy-samsung-ufs.h"

#define TENSOR_GS101_PHY_CTRL		0x3ec8
#define TENSOR_GS101_PHY_CTRL_MASK	0x1
#define TENSOR_GS101_PHY_CTRL_EN	BIT(0)
#define PHY_GS101_LANE_OFFSET		0x200
#define TRSV_REG338			0x338
#define LN0_MON_RX_CAL_DONE		BIT(3)
#define TRSV_REG339			0x339
#define LN0_MON_RX_CDR_FLD_CK_MODE_DONE BIT(3)
#define TRSV_REG222			0x222
#define LN0_OVRD_RX_CDR_EN		BIT(4)
#define LN0_RX_CDR_EN			BIT(3)

#define PHY_PMA_TRSV_ADDR(reg, lane)	(PHY_APB_ADDR((reg) + \
					((lane) * PHY_GS101_LANE_OFFSET)))

#define PHY_TRSV_REG_CFG_GS101(o, v, d) \
	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_GS101_LANE_OFFSET)

/* Calibration for phy initialization */
static const struct samsung_ufs_phy_cfg tensor_gs101_pre_init_cfg[] = {
	PHY_COMN_REG_CFG(0x43, 0x10,  PWR_MODE_ANY),
	PHY_COMN_REG_CFG(0x3C, 0x14,  PWR_MODE_ANY),
	PHY_COMN_REG_CFG(0x46, 0x48,  PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x200, 0x00, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x201, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x202, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x203, 0x0a, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x204, 0x00, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x205, 0x11, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x207, 0x0c, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2E1, 0xc0, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x22D, 0xb8, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x234, 0x60, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x238, 0x13, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x239, 0x48, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23A, 0x01, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23B, 0x25, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23C, 0x2a, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23D, 0x01, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23E, 0x13, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x23F, 0x13, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x240, 0x4a, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x243, 0x40, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x244, 0x02, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x25D, 0x00, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x25E, 0x3f, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x25F, 0xff, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x273, 0x33, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x274, 0x50, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x284, 0x02, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x285, 0x02, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2A2, 0x04, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x25D, 0x01, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2FA, 0x01, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x286, 0x03, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x287, 0x03, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x288, 0x03, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x289, 0x03, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2B3, 0x04, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2B6, 0x0b, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2B7, 0x0b, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2B8, 0x0b, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2B9, 0x0b, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2BA, 0x0b, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2BB, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2BC, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2BD, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x29E, 0x06, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2E4, 0x1a, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2ED, 0x25, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x269, 0x1a, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x2F4, 0x2f, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x34B, 0x01, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x34C, 0x23, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x34D, 0x23, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x34E, 0x45, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x34F, 0x00, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x350, 0x31, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x351, 0x00, PWR_MODE_ANY),
	PHY_TRSV_REG_CFG_GS101(0x352, 0x02, PWR_MODE_ANY),

Annotation

Implementation Notes