drivers/phy/samsung/phy-s5pv210-usb2.c

Source file repositories/reference/linux-study-clean/drivers/phy/samsung/phy-s5pv210-usb2.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/samsung/phy-s5pv210-usb2.c
Extension
.c
Size
4441 bytes
Lines
189
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 * Authors: Kamil Debski <k.debski@samsung.com>
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/phy/phy.h>
#include "phy-samsung-usb2.h"

/* Exynos USB PHY registers */

/* PHY power control */
#define S5PV210_UPHYPWR			0x0

#define S5PV210_UPHYPWR_PHY0_SUSPEND	BIT(0)
#define S5PV210_UPHYPWR_PHY0_PWR	BIT(3)
#define S5PV210_UPHYPWR_PHY0_OTG_PWR	BIT(4)
#define S5PV210_UPHYPWR_PHY0	( \
	S5PV210_UPHYPWR_PHY0_SUSPEND | \
	S5PV210_UPHYPWR_PHY0_PWR | \
	S5PV210_UPHYPWR_PHY0_OTG_PWR)

#define S5PV210_UPHYPWR_PHY1_SUSPEND	BIT(6)
#define S5PV210_UPHYPWR_PHY1_PWR	BIT(7)
#define S5PV210_UPHYPWR_PHY1 ( \
	S5PV210_UPHYPWR_PHY1_SUSPEND | \
	S5PV210_UPHYPWR_PHY1_PWR)

/* PHY clock control */
#define S5PV210_UPHYCLK			0x4

#define S5PV210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
#define S5PV210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
#define S5PV210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
#define S5PV210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)

#define S5PV210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
#define S5PV210_UPHYCLK_PHY0_COMMON_ON	BIT(4)
#define S5PV210_UPHYCLK_PHY1_COMMON_ON	BIT(7)

/* PHY reset control */
#define S5PV210_UPHYRST			0x8

#define S5PV210_URSTCON_PHY0		BIT(0)
#define S5PV210_URSTCON_OTG_HLINK	BIT(1)
#define S5PV210_URSTCON_OTG_PHYLINK	BIT(2)
#define S5PV210_URSTCON_PHY1_ALL	BIT(3)
#define S5PV210_URSTCON_HOST_LINK_ALL	BIT(4)

/* Isolation, configured in the power management unit */
#define S5PV210_USB_ISOL_OFFSET		0x680c
#define S5PV210_USB_ISOL_DEVICE		BIT(0)
#define S5PV210_USB_ISOL_HOST		BIT(1)


enum s5pv210_phy_id {
	S5PV210_DEVICE,
	S5PV210_HOST,
	S5PV210_NUM_PHYS,
};

/*
 * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
 * can be written to the phy register.
 */
static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
{
	switch (rate) {
	case 12 * MHZ:
		*reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
		break;
	case 24 * MHZ:
		*reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
		break;
	case 48 * MHZ:
		*reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
{

Annotation

Implementation Notes