drivers/phy/socionext/phy-uniphier-ahci.c

Source file repositories/reference/linux-study-clean/drivers/phy/socionext/phy-uniphier-ahci.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/socionext/phy-uniphier-ahci.c
Extension
.c
Size
13382 bytes
Lines
515
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct uniphier_ahciphy_priv {
	struct device *dev;
	void __iomem  *base;
	struct clk *clk, *clk_parent, *clk_parent_gio;
	struct reset_control *rst, *rst_parent, *rst_parent_gio;
	struct reset_control *rst_pm, *rst_tx, *rst_rx;
	const struct uniphier_ahciphy_soc_data *data;
};

struct uniphier_ahciphy_soc_data {
	int (*init)(struct uniphier_ahciphy_priv *priv);
	int (*power_on)(struct uniphier_ahciphy_priv *priv);
	int (*power_off)(struct uniphier_ahciphy_priv *priv);
	bool is_legacy;
	bool is_ready_high;
	bool is_phy_clk;
};

/* for Pro4 */
#define CKCTRL0				0x0
#define CKCTRL0_CK_OFF			BIT(9)
#define CKCTRL0_NCY_MASK		GENMASK(8, 4)
#define CKCTRL0_NCY5_MASK		GENMASK(3, 2)
#define CKCTRL0_PRESCALE_MASK		GENMASK(1, 0)
#define CKCTRL1				0x4
#define CKCTRL1_LOS_LVL_MASK		GENMASK(20, 16)
#define CKCTRL1_TX_LVL_MASK		GENMASK(12, 8)
#define RXTXCTRL			0x8
#define RXTXCTRL_RX_EQ_VALL_MASK	GENMASK(31, 29)
#define RXTXCTRL_RX_DPLL_MODE_MASK	GENMASK(28, 26)
#define RXTXCTRL_TX_ATTEN_MASK		GENMASK(14, 12)
#define RXTXCTRL_TX_BOOST_MASK		GENMASK(11, 8)
#define RXTXCTRL_TX_EDGERATE_MASK	GENMASK(3, 2)
#define RXTXCTRL_TX_CKO_EN		BIT(0)
#define RSTPWR				0x30
#define RSTPWR_RX_EN_VAL		BIT(18)

/* for PXs2/PXs3 */
#define CKCTRL				0x0
#define CKCTRL_P0_READY			BIT(15)
#define CKCTRL_P0_RESET			BIT(10)
#define CKCTRL_REF_SSP_EN		BIT(9)
#define TXCTRL0				0x4
#define TXCTRL0_AMP_G3_MASK		GENMASK(22, 16)
#define TXCTRL0_AMP_G2_MASK		GENMASK(14, 8)
#define TXCTRL0_AMP_G1_MASK		GENMASK(6, 0)
#define TXCTRL1				0x8
#define TXCTRL1_DEEMPH_G3_MASK		GENMASK(21, 16)
#define TXCTRL1_DEEMPH_G2_MASK		GENMASK(13, 8)
#define TXCTRL1_DEEMPH_G1_MASK		GENMASK(5, 0)
#define RXCTRL				0xc
#define RXCTRL_LOS_LVL_MASK		GENMASK(20, 16)
#define RXCTRL_LOS_BIAS_MASK		GENMASK(10, 8)
#define RXCTRL_RX_EQ_MASK		GENMASK(2, 0)

static int uniphier_ahciphy_pro4_init(struct uniphier_ahciphy_priv *priv)
{
	u32 val;

	/* set phy MPLL parameters */
	val = readl(priv->base + CKCTRL0);
	val &= ~CKCTRL0_NCY_MASK;
	val |= FIELD_PREP(CKCTRL0_NCY_MASK, 0x6);
	val &= ~CKCTRL0_NCY5_MASK;
	val |= FIELD_PREP(CKCTRL0_NCY5_MASK, 0x2);
	val &= ~CKCTRL0_PRESCALE_MASK;
	val |= FIELD_PREP(CKCTRL0_PRESCALE_MASK, 0x1);
	writel(val, priv->base + CKCTRL0);

	/* setup phy control parameters */
	val = readl(priv->base + CKCTRL1);
	val &= ~CKCTRL1_LOS_LVL_MASK;
	val |= FIELD_PREP(CKCTRL1_LOS_LVL_MASK, 0x10);
	val &= ~CKCTRL1_TX_LVL_MASK;
	val |= FIELD_PREP(CKCTRL1_TX_LVL_MASK, 0x06);
	writel(val, priv->base + CKCTRL1);

	val = readl(priv->base + RXTXCTRL);
	val &= ~RXTXCTRL_RX_EQ_VALL_MASK;
	val |= FIELD_PREP(RXTXCTRL_RX_EQ_VALL_MASK, 0x6);
	val &= ~RXTXCTRL_RX_DPLL_MODE_MASK;
	val |= FIELD_PREP(RXTXCTRL_RX_DPLL_MODE_MASK, 0x3);
	val &= ~RXTXCTRL_TX_ATTEN_MASK;
	val |= FIELD_PREP(RXTXCTRL_TX_ATTEN_MASK, 0x3);
	val &= ~RXTXCTRL_TX_BOOST_MASK;
	val |= FIELD_PREP(RXTXCTRL_TX_BOOST_MASK, 0x5);
	val &= ~RXTXCTRL_TX_EDGERATE_MASK;
	val |= FIELD_PREP(RXTXCTRL_TX_EDGERATE_MASK, 0x0);
	writel(val, priv->base + RXTXCTRL);

Annotation

Implementation Notes