drivers/phy/spacemit/phy-k1-pcie.c

Source file repositories/reference/linux-study-clean/drivers/phy/spacemit/phy-k1-pcie.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/spacemit/phy-k1-pcie.c
Extension
.c
Size
19877 bytes
Lines
671
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct k1_pcie_phy {
	struct device *dev;		/* PHY provider device */
	struct phy *phy;
	void __iomem *regs;
	u32 pcie_lanes;			/* Max (1 or 2) unless limited by DT */
	struct clk *pll;
	struct clk_hw pll_hw;		/* Private PLL clock */

	/* The remaining fields are only used for the combo PHY */
	u32 type;			/* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
	struct regmap *pmu;		/* MMIO regmap (no errors) */
};

#define CALIBRATION_TIMEOUT		500000	/* For combo PHY (usec) */
#define PLL_TIMEOUT			500000	/* For PHY PLL lock (usec) */
#define POLL_DELAY			500	/* Time between polls (usec) */

/* Selecting the combo PHY operating mode requires APMU regmap access */
#define SYSCON_APMU			"spacemit,apmu"

/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */

#define PMUA_USB_PHY_CTRL0			0x0110
#define COMBO_PHY_SEL			BIT(3)	/* 0: PCIe; 1: USB 3 */

#define PCIE_CLK_RES_CTRL			0x03cc
#define PCIE_APP_HOLD_PHY_RST		BIT(30)

/* PHY register space */

/* Offset between lane 0 and lane 1 registers when there are two */
#define PHY_LANE_OFFSET				0x0400

/* PHY PLL configuration */
#define PCIE_PU_ADDR_CLK_CFG			0x0008
#define PLL_READY			BIT(0)		/* read-only */
#define CFG_INTERNAL_TIMER_ADJ		GENMASK(10, 7)
#define TIMER_ADJ_USB		0x2
#define TIMER_ADJ_PCIE		0x6
#define CFG_SW_PHY_INIT_DONE		BIT(11)	/* We set after PLL config */

#define PCIE_RC_DONE_STATUS			0x0018
#define CFG_FORCE_RCV_RETRY		BIT(10)		/* Used for PCIe */

/* PCIe PHY lane calibration; assumes 24MHz input clock */
#define PCIE_RC_CAL_REG2			0x0020
#define RC_CAL_TOGGLE			BIT(22)
#define CLKSEL				GENMASK(31, 29)
#define CLKSEL_24M		0x3

/* Additional PHY PLL configuration (USB 3 and PCIe) */
#define PCIE_PU_PLL_1				0x0048
#define REF_100_WSSC			BIT(12)	/* 1: input is 100MHz, SSC */
#define FREF_SEL			GENMASK(15, 13)
#define FREF_24M		0x1
#define SSC_DEP_SEL			GENMASK(19, 16)
#define SSC_DEP_NONE		0x0
#define SSC_DEP_5000PPM		0xa

/* PCIe PHY configuration */
#define PCIE_PU_PLL_2				0x004c
#define GEN_REF100			BIT(4)	/* 1: generate 100MHz clk */

#define PCIE_RX_REG1				0x0050
#define EN_RTERM			BIT(3)
#define AFE_RTERM_REG			GENMASK(11, 8)

#define PCIE_RX_REG2				0x0054
#define RX_RTERM_SEL			BIT(5)	/* 0: use AFE_RTERM_REG value */

#define PCIE_LTSSM_DIS_ENTRY			0x005c
#define CFG_REFCLK_MODE			GENMASK(9, 8)
#define RFCLK_MODE_DRIVER	0x1
#define OVRD_REFCLK_MODE		BIT(10)	/* 1: use CFG_RFCLK_MODE */

#define PCIE_TX_REG1				0x0064
#define TX_RTERM_REG			GENMASK(15, 12)
#define TX_RTERM_SEL			BIT(25)	/* 1: use TX_RTERM_REG */

/* Zeroed for the combo PHY operating in USB mode */
#define USB3_TEST_CTRL				0x0068

/* PHY calibration values, determined by the combo PHY at probe time */
#define PCIE_RCAL_RESULT			0x0084	/* Port A PHY only */
#define RTERM_VALUE_RX			GENMASK(3, 0)
#define RTERM_VALUE_TX			GENMASK(7, 4)
#define R_TUNE_DONE			BIT(10)

static u32 k1_phy_rterm = ~0;     /* Invalid initial value */

Annotation

Implementation Notes