drivers/phy/starfive/phy-jh7110-dphy-rx.c

Source file repositories/reference/linux-study-clean/drivers/phy/starfive/phy-jh7110-dphy-rx.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/starfive/phy-jh7110-dphy-rx.c
Extension
.c
Size
6270 bytes
Lines
228
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct stf_dphy_info {
	/**
	 * @maps:
	 *
	 * Physical lanes and logic lanes mapping table.
	 *
	 * The default order is:
	 * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
	 */
	u8 maps[STF_MAP_LANES_NUM];
};

struct stf_dphy {
	struct device *dev;
	void __iomem *regs;
	struct clk *cfg_clk;
	struct clk *ref_clk;
	struct clk *tx_clk;
	struct reset_control *rstc;
	struct regulator *mipi_0p9;
	struct phy *phy;
	const struct stf_dphy_info *info;
};

static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
{
	struct stf_dphy *dphy = phy_get_drvdata(phy);
	const struct stf_dphy_info *info = dphy->info;

	writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) |
	       FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) |
	       FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) |
	       FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) |
	       FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) |
	       FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) |
	       FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) |
	       FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) |
	       FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) |
	       FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]),
	       dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188));

	writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) |
	       FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, info->maps[4]) |
	       FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8),
	       dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192));

	writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) |
	       FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) |
	       FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) |
	       FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7),
	       dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196));

	writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7),
	       dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200));

	return 0;
}

static int stf_dphy_power_on(struct phy *phy)
{
	struct stf_dphy *dphy = phy_get_drvdata(phy);
	int ret;

	ret = pm_runtime_resume_and_get(dphy->dev);
	if (ret < 0)
		return ret;

	ret = regulator_enable(dphy->mipi_0p9);
	if (ret) {
		pm_runtime_put(dphy->dev);
		return ret;
	}

	clk_set_rate(dphy->cfg_clk, 99000000);
	clk_set_rate(dphy->ref_clk, 49500000);
	clk_set_rate(dphy->tx_clk, 19800000);
	reset_control_deassert(dphy->rstc);

	return 0;
}

static int stf_dphy_power_off(struct phy *phy)
{
	struct stf_dphy *dphy = phy_get_drvdata(phy);

	reset_control_assert(dphy->rstc);

	regulator_disable(dphy->mipi_0p9);

	pm_runtime_put_sync(dphy->dev);

Annotation

Implementation Notes