drivers/phy/starfive/phy-jh7110-pcie.c

Source file repositories/reference/linux-study-clean/drivers/phy/starfive/phy-jh7110-pcie.c

File Facts

System
Linux kernel
Corpus path
drivers/phy/starfive/phy-jh7110-pcie.c
Extension
.c
Size
5342 bytes
Lines
205
Domain
Driver Families
Bucket
drivers/phy
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct jh7110_pcie_phy {
	struct phy *phy;
	struct regmap *stg_syscon;
	struct regmap *sys_syscon;
	void __iomem *regs;
	u32 sys_phy_connect;
	u32 stg_pcie_mode;
	u32 stg_pcie_usb;
	enum phy_mode mode;
};

static int phy_usb3_mode_set(struct jh7110_pcie_phy *data)
{
	if (!data->stg_syscon || !data->sys_syscon) {
		dev_err(&data->phy->dev, "doesn't support usb3 mode\n");
		return -EINVAL;
	}

	regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
			   PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
			   PCIE_USB3_BUS_WIDTH_MASK, 0);
	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
			   PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);

	/* Connect usb 3.0 phy mode */
	regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
			   USB_PDRSTN_SPLIT, 0);

	/* Configuare spread-spectrum mode: down-spread-spectrum */
	writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);

	return 0;
}

static void phy_pcie_mode_set(struct jh7110_pcie_phy *data)
{
	u32 val;

	/* default is PCIe mode */
	if (!data->stg_syscon || !data->sys_syscon)
		return;

	regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
			   PCIE_PHY_MODE_MASK, 0);
	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
			   PCIE_USB3_BUS_WIDTH_MASK,
			   PCIE_USB3_BUS_WIDTH);
	regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
			   PCIE_USB3_PHY_ENABLE, 0);

	regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
			   USB_PDRSTN_SPLIT, 0);

	val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
	val &= ~PCIE_USB3_PHY_ENABLE;
	writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
}

static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
{
	/* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
	writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
	writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
}

static int jh7110_pcie_phy_set_mode(struct phy *_phy,
				    enum phy_mode mode, int submode)
{
	struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
	int ret;

	if (mode == phy->mode)
		return 0;

	switch (mode) {
	case PHY_MODE_USB_HOST:
	case PHY_MODE_USB_DEVICE:
	case PHY_MODE_USB_OTG:
		ret = phy_usb3_mode_set(phy);
		if (ret)
			return ret;
		break;
	case PHY_MODE_PCIE:
		phy_pcie_mode_set(phy);
		break;
	default:
		return -EINVAL;
	}

Annotation

Implementation Notes