drivers/pinctrl/actions/pinctrl-s900.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/actions/pinctrl-s900.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/actions/pinctrl-s900.c
Extension
.c
Size
56304 bytes
Lines
1830
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * OWL S900 Pinctrl driver
 *
 * Copyright (c) 2014 Actions Semi Inc.
 * Author: David Liu <liuwei@actions-semi.com>
 *
 * Copyright (c) 2018 Linaro Ltd.
 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-owl.h"

/* Pinctrl registers offset */
#define MFCTL0			(0x0040)
#define MFCTL1			(0x0044)
#define MFCTL2			(0x0048)
#define MFCTL3			(0x004C)
#define PAD_PULLCTL0		(0x0060)
#define PAD_PULLCTL1		(0x0064)
#define PAD_PULLCTL2		(0x0068)
#define PAD_ST0			(0x006C)
#define PAD_ST1			(0x0070)
#define PAD_CTL			(0x0074)
#define PAD_DRV0		(0x0080)
#define PAD_DRV1		(0x0084)
#define PAD_DRV2		(0x0088)
#define PAD_SR0			(0x0270)
#define PAD_SR1			(0x0274)
#define PAD_SR2			(0x0278)

#define _GPIOA(offset)		(offset)
#define _GPIOB(offset)		(32 + (offset))
#define _GPIOC(offset)		(64 + (offset))
#define _GPIOD(offset)		(76 + (offset))
#define _GPIOE(offset)		(106 + (offset))
#define _GPIOF(offset)		(138 + (offset))

#define NUM_GPIOS		(_GPIOF(7) + 1)
#define _PIN(offset)		(NUM_GPIOS + (offset))

#define ETH_TXD0		_GPIOA(0)
#define ETH_TXD1		_GPIOA(1)
#define ETH_TXEN		_GPIOA(2)
#define ETH_RXER		_GPIOA(3)
#define ETH_CRS_DV		_GPIOA(4)
#define ETH_RXD1		_GPIOA(5)
#define ETH_RXD0		_GPIOA(6)
#define ETH_REF_CLK		_GPIOA(7)
#define ETH_MDC			_GPIOA(8)
#define ETH_MDIO		_GPIOA(9)
#define SIRQ0			_GPIOA(10)
#define SIRQ1			_GPIOA(11)
#define SIRQ2			_GPIOA(12)
#define I2S_D0			_GPIOA(13)
#define I2S_BCLK0		_GPIOA(14)
#define I2S_LRCLK0		_GPIOA(15)
#define I2S_MCLK0		_GPIOA(16)
#define I2S_D1			_GPIOA(17)
#define I2S_BCLK1		_GPIOA(18)
#define I2S_LRCLK1		_GPIOA(19)
#define I2S_MCLK1		_GPIOA(20)
#define ERAM_A5			_GPIOA(21)
#define ERAM_A6			_GPIOA(22)
#define ERAM_A7			_GPIOA(23)
#define ERAM_A8			_GPIOA(24)
#define ERAM_A9			_GPIOA(25)
#define ERAM_A10		_GPIOA(26)
#define ERAM_A11		_GPIOA(27)
#define SD0_D0			_GPIOA(28)
#define SD0_D1			_GPIOA(29)
#define SD0_D2			_GPIOA(30)
#define SD0_D3			_GPIOA(31)

#define SD1_D0			_GPIOB(0)
#define SD1_D1			_GPIOB(1)
#define SD1_D2			_GPIOB(2)
#define SD1_D3			_GPIOB(3)
#define SD0_CMD			_GPIOB(4)
#define SD0_CLK			_GPIOB(5)
#define SD1_CMD			_GPIOB(6)
#define SD1_CLK			_GPIOB(7)
#define SPI0_SCLK		_GPIOB(8)
#define SPI0_SS			_GPIOB(9)
#define SPI0_MISO		_GPIOB(10)

Annotation

Implementation Notes