drivers/pinctrl/aspeed/Kconfig

Source file repositories/reference/linux-study-clean/drivers/pinctrl/aspeed/Kconfig

File Facts

System: Linux kernel
Corpus path: drivers/pinctrl/aspeed/Kconfig
Extension: [no extension]
Size: 1722 bytes
Lines: 57
Domain: Driver Families
Bucket: drivers/pinctrl
Inferred role: Driver Families: build/configuration rule
Status: atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_ASPEED
	bool
	depends on (ARCH_ASPEED || COMPILE_TEST) && OF
	select MFD_SYSCON
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	select REGMAP_MMIO

config PINCTRL_ASPEED_G4
	bool "Aspeed G4 SoC pin control"
	depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF
	select PINCTRL_ASPEED
	help
	  Say Y here to enable pin controller support for Aspeed's 4th
	  generation SoCs. GPIO is provided by a separate GPIO driver.

config PINCTRL_ASPEED_G5
	bool "Aspeed G5 SoC pin control"
	depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
	select PINCTRL_ASPEED
	help
	  Say Y here to enable pin controller support for Aspeed's 5th
	  generation SoCs. GPIO is provided by a separate GPIO driver.

config PINCTRL_ASPEED_G6
	bool "Aspeed G6 SoC pin control"
	depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
	select PINCTRL_ASPEED
	help
	  Say Y here to enable pin controller support for Aspeed's 6th
	  generation SoCs. GPIO is provided by a separate GPIO driver.

config PINCTRL_ASPEED_G7_SOC0
	bool "Aspeed G7 SoC pin control"
	depends on (ARCH_ASPEED || COMPILE_TEST) && OF
	select PINCTRL_ASPEED
	help
	  Say Y here to enable pin controller support for the SoC0 instance
	  of Aspeed's 7th generation SoCs. GPIO is provided by a separate
	  GPIO driver.

config PINCTRL_ASPEED_G7_SOC1
	bool "Aspeed G7 SoC1 pin control"
	depends on (ARCH_ASPEED || COMPILE_TEST) && OF
	select MFD_SYSCON
	select PINMUX
	select GENERIC_PINCTRL_GROUPS
	select GENERIC_PINMUX_FUNCTIONS
	select GENERIC_PINCONF
	select REGMAP_MMIO
	help
	  Say Y here to enable pin controller support for the SoC1 instance
	  of Aspeed's 7th generation SoCs. GPIO is provided by a separate
	  GPIO driver.

Annotation

Atlas domain: Driver Families / drivers/pinctrl.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.