drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
Extension
.c
Size
93317 bytes
Lines
2812
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (is_strap) {
			/*
			 * The AST2600 has write protection mask registers for
			 * the hardware strapping in SCU508 and SCU518. Assume
			 * that if the platform doesn't want the strapping
			 * values changed that it has set the write mask.
			 *
			 * The strapping registers implement write-1-clear
			 * behaviour. SCU500 is paired with clear writes on
			 * SCU504, likewise SCU510 is paired with SCU514.
			 */
			u32 clear = ~val & desc->mask;
			u32 w1c = desc->reg + 4;

			if (clear)
				ret = regmap_update_bits(ctx->maps[desc->ip],
							 w1c, desc->mask,
							 clear);
		}

		ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
					 desc->mask, val);
		if (ret)
			return ret;
	}

	ret = aspeed_sig_expr_eval(ctx, expr, enable);
	if (ret < 0)
		return ret;

	if (!ret)
		return -EPERM;
	return 0;
}

static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
	{ PIN_CONFIG_BIAS_PULL_DOWN,  0,   1, BIT_MASK(0)},
	{ PIN_CONFIG_BIAS_PULL_DOWN, -1,   0, BIT_MASK(0)},
	{ PIN_CONFIG_BIAS_PULL_UP,    0,   1, BIT_MASK(0)},
	{ PIN_CONFIG_BIAS_PULL_UP,   -1,   0, BIT_MASK(0)},
	{ PIN_CONFIG_BIAS_DISABLE,   -1,   1, BIT_MASK(0)},
	{ PIN_CONFIG_DRIVE_STRENGTH,  4,   0, GENMASK(1, 0)},
	{ PIN_CONFIG_DRIVE_STRENGTH,  8,   1, GENMASK(1, 0)},
	{ PIN_CONFIG_DRIVE_STRENGTH, 12,   2, GENMASK(1, 0)},
	{ PIN_CONFIG_DRIVE_STRENGTH, 16,   3, GENMASK(1, 0)},
	{ PIN_CONFIG_POWER_SOURCE,   3300, 0, BIT_MASK(0)},
	{ PIN_CONFIG_POWER_SOURCE,   1800, 1, BIT_MASK(0)},
};

static const struct aspeed_pinmux_ops aspeed_g5_ops = {
	.set = aspeed_g6_sig_expr_set,
};

static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
	.pins = aspeed_g6_pins,
	.npins = ARRAY_SIZE(aspeed_g6_pins),
	.pinmux = {
		.ops = &aspeed_g5_ops,
		.groups = aspeed_g6_groups,
		.ngroups = ARRAY_SIZE(aspeed_g6_groups),
		.functions = aspeed_g6_functions,
		.nfunctions = ARRAY_SIZE(aspeed_g6_functions),
	},
	.configs = aspeed_g6_configs,
	.nconfigs = ARRAY_SIZE(aspeed_g6_configs),
	.confmaps = aspeed_g6_pin_config_map,
	.nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
};

static const struct pinmux_ops aspeed_g6_pinmux_ops = {
	.get_functions_count = aspeed_pinmux_get_fn_count,
	.get_function_name = aspeed_pinmux_get_fn_name,
	.get_function_groups = aspeed_pinmux_get_fn_groups,
	.set_mux = aspeed_pinmux_set_mux,
	.gpio_request_enable = aspeed_gpio_request_enable,
	.strict = true,
};

static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
	.get_groups_count = aspeed_pinctrl_get_groups_count,
	.get_group_name = aspeed_pinctrl_get_group_name,
	.get_group_pins = aspeed_pinctrl_get_group_pins,
	.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
	.dt_free_map = pinctrl_utils_free_map,
};

static const struct pinconf_ops aspeed_g6_conf_ops = {
	.is_generic = true,
	.pin_config_get = aspeed_pin_config_get,

Annotation

Implementation Notes