drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
Extension
.c
Size
31634 bytes
Lines
750
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0

#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#include "pinctrl-aspeed.h"
#include "pinmux-aspeed.h"
#include "../pinctrl-utils.h"

#define SCU200 0x200 /* System Reset Control #1  */

#define SCU010 0x010 /* Hardware Strap Register */
#define SCU400 0x400 /* Multi-function Pin Control #1  */
#define SCU404 0x404 /* Multi-function Pin Control #2  */
#define SCU408 0x408 /* Multi-function Pin Control #3  */
#define SCU40C 0x40C /* Multi-function Pin Control #3  */
#define SCU410 0x410 /* USB Multi-function Control Register  */
#define SCU414 0x414 /* VGA Function Control Register  */

#define SCU480 0x480 /* GPIO18A0 IO Control Register */
#define SCU484 0x484 /* GPIO18A1 IO Control Register */
#define SCU488 0x488 /* GPIO18A2 IO Control Register */
#define SCU48C 0x48c /* GPIO18A3 IO Control Register */
#define SCU490 0x490 /* GPIO18A4 IO Control Register */
#define SCU494 0x494 /* GPIO18A5 IO Control Register */
#define SCU498 0x498 /* GPIO18A6 IO Control Register */
#define SCU49C 0x49c /* GPIO18A7 IO Control Register */
#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */
#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */
#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */
#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */

enum {
	AC14,
	AE15,
	AD14,
	AE14,
	AF14,
	AB13,
	AB14,
	AF15,
	AF13,
	AC13,
	AD13,
	AE13,
	JTAG_PORT,
	PCIERC0_PERST,
	PCIERC1_PERST,
	PORTA_MODE,
	PORTA_U2,
	PORTB_MODE,
	PORTB_U2,
	PORTA_U2_PHY,
	PORTB_U2_PHY,
	PORTA_U3,
	PORTB_U3,
	PORTA_U3_PHY,
	PORTB_U3_PHY,
};

SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0));
SIG_EXPR_LIST_DECL_SEMG(AC14, VB1CS, VB1, VB, SIG_DESC_SET(SCU404, 0));
PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS);

SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1));
SIG_EXPR_LIST_DECL_SEMG(AE15, VB1CK, VB1, VB, SIG_DESC_SET(SCU404, 1));
PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK);

SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2));
SIG_EXPR_LIST_DECL_SEMG(AD14, VB1MOSI, VB1, VB, SIG_DESC_SET(SCU404, 2));
PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI);

SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3));
SIG_EXPR_LIST_DECL_SEMG(AE14, VB1MISO, VB1, VB, SIG_DESC_SET(SCU404, 3));
PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO);

SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4));
PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2);

SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5));
PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3);

Annotation

Implementation Notes