drivers/pinctrl/cirrus/pinctrl-cs42l43.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/cirrus/pinctrl-cs42l43.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/cirrus/pinctrl-cs42l43.c- Extension
.c- Size
- 16844 bytes
- Lines
- 622
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/bits.hlinux/build_bug.hlinux/err.hlinux/gpio/driver.hlinux/mfd/cs42l43.hlinux/mfd/cs42l43-regs.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/regmap.hlinux/string_choices.hlinux/pinctrl/consumer.hlinux/pinctrl/pinctrl.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinconf-generic.hlinux/pinctrl/pinmux.h../pinctrl-utils.h
Detected Declarations
struct cs42l43_pinstruct cs42l43_pin_dataenum cs42l43_pin_funcsfunction cs42l43_pin_get_groups_countfunction cs42l43_pin_get_group_pinsfunction cs42l43_pin_get_func_countfunction cs42l43_pin_get_func_groupsfunction cs42l43_pin_set_muxfunction cs42l43_gpio_set_directionfunction cs42l43_gpio_request_enablefunction cs42l43_gpio_disable_freefunction cs42l43_pin_get_drv_strfunction cs42l43_pin_set_drv_strfunction cs42l43_pin_get_dbfunction cs42l43_pin_set_dbfunction cs42l43_pin_config_getfunction cs42l43_pin_config_setfunction cs42l43_pin_config_group_getfunction cs42l43_pin_config_group_setfunction cs42l43_gpio_getfunction cs42l43_gpio_setfunction cs42l43_gpio_direction_outfunction cs42l43_gpio_add_pin_rangesfunction cs42l43_fwnode_putfunction cs42l43_pin_probe
Annotated Snippet
struct cs42l43_pin {
struct gpio_chip gpio_chip;
struct device *dev;
struct regmap *regmap;
bool shutters_locked;
};
struct cs42l43_pin_data {
unsigned int reg;
unsigned int shift;
unsigned int mask;
};
#define CS42L43_PIN(_number, _name, _reg, _field) { \
.number = _number, .name = _name, \
.drv_data = &((struct cs42l43_pin_data){ \
.reg = CS42L43_##_reg, \
.shift = CS42L43_##_field##_DRV_SHIFT, \
.mask = CS42L43_##_field##_DRV_MASK, \
}), \
}
static const struct pinctrl_pin_desc cs42l43_pin_pins[] = {
CS42L43_PIN(0, "gpio1", DRV_CTRL4, GPIO1),
CS42L43_PIN(1, "gpio2", DRV_CTRL4, GPIO2),
CS42L43_PIN(2, "gpio3", DRV_CTRL4, GPIO3),
CS42L43_PIN(3, "asp_dout", DRV_CTRL1, ASP_DOUT),
CS42L43_PIN(4, "asp_fsync", DRV_CTRL1, ASP_FSYNC),
CS42L43_PIN(5, "asp_bclk", DRV_CTRL1, ASP_BCLK),
CS42L43_PIN(6, "pdmout2_clk", DRV_CTRL3, PDMOUT2_CLK),
CS42L43_PIN(7, "pdmout2_data", DRV_CTRL3, PDMOUT2_DATA),
CS42L43_PIN(8, "pdmout1_clk", DRV_CTRL3, PDMOUT1_CLK),
CS42L43_PIN(9, "pdmout1_data", DRV_CTRL3, PDMOUT1_DATA),
CS42L43_PIN(10, "i2c_sda", DRV_CTRL3, I2C_SDA),
CS42L43_PIN(11, "i2c_scl", DRV_CTRL_5, I2C_SCL),
CS42L43_PIN(12, "spi_miso", DRV_CTRL3, SPI_MISO),
CS42L43_PIN(13, "spi_sck", DRV_CTRL_5, SPI_SCK),
CS42L43_PIN(14, "spi_ssb", DRV_CTRL_5, SPI_SSB),
};
static const unsigned int cs42l43_pin_gpio1_pins[] = { 0 };
static const unsigned int cs42l43_pin_gpio2_pins[] = { 1 };
static const unsigned int cs42l43_pin_gpio3_pins[] = { 2 };
static const unsigned int cs42l43_pin_asp_pins[] = { 3, 4, 5 };
static const unsigned int cs42l43_pin_pdmout2_pins[] = { 6, 7 };
static const unsigned int cs42l43_pin_pdmout1_pins[] = { 8, 9 };
static const unsigned int cs42l43_pin_i2c_pins[] = { 10, 11 };
static const unsigned int cs42l43_pin_spi_pins[] = { 12, 13, 14 };
#define CS42L43_PINGROUP(_name) \
PINCTRL_PINGROUP(#_name, cs42l43_pin_##_name##_pins, \
ARRAY_SIZE(cs42l43_pin_##_name##_pins))
static const struct pingroup cs42l43_pin_groups[] = {
CS42L43_PINGROUP(gpio1),
CS42L43_PINGROUP(gpio2),
CS42L43_PINGROUP(gpio3),
CS42L43_PINGROUP(asp),
CS42L43_PINGROUP(pdmout2),
CS42L43_PINGROUP(pdmout1),
CS42L43_PINGROUP(i2c),
CS42L43_PINGROUP(spi),
};
static int cs42l43_pin_get_groups_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(cs42l43_pin_groups);
}
static const char *cs42l43_pin_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group_idx)
{
return cs42l43_pin_groups[group_idx].name;
}
static int cs42l43_pin_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group_idx,
const unsigned int **pins,
unsigned int *num_pins)
{
*pins = cs42l43_pin_groups[group_idx].pins;
*num_pins = cs42l43_pin_groups[group_idx].npins;
return 0;
}
static const struct pinctrl_ops cs42l43_pin_group_ops = {
.get_groups_count = cs42l43_pin_get_groups_count,
.get_group_name = cs42l43_pin_get_group_name,
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/bits.h`, `linux/build_bug.h`, `linux/err.h`, `linux/gpio/driver.h`, `linux/mfd/cs42l43.h`, `linux/mfd/cs42l43-regs.h`, `linux/module.h`.
- Detected declarations: `struct cs42l43_pin`, `struct cs42l43_pin_data`, `enum cs42l43_pin_funcs`, `function cs42l43_pin_get_groups_count`, `function cs42l43_pin_get_group_pins`, `function cs42l43_pin_get_func_count`, `function cs42l43_pin_get_func_groups`, `function cs42l43_pin_set_mux`, `function cs42l43_gpio_set_direction`, `function cs42l43_gpio_request_enable`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.