drivers/pinctrl/intel/pinctrl-cannonlake.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/intel/pinctrl-cannonlake.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/intel/pinctrl-cannonlake.c
Extension
.c
Size
28304 bytes
Lines
834
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Cannon Lake PCH pinctrl/GPIO driver
 *
 * Copyright (C) 2017 Intel Corporation
 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-intel.h"

#define CNL_LP_PAD_OWN		0x020
#define CNL_LP_PADCFGLOCK	0x080
#define CNL_LP_HOSTSW_OWN	0x0b0
#define CNL_LP_GPI_IS		0x100
#define CNL_LP_GPI_IE		0x120

#define CNL_H_PAD_OWN		0x020
#define CNL_H_PADCFGLOCK	0x080
#define CNL_H_HOSTSW_OWN	0x0c0
#define CNL_H_GPI_IS		0x100
#define CNL_H_GPI_IE		0x120

#define CNL_LP_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)

#define CNL_H_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H)

/* Cannon Lake-H */
static const struct pinctrl_pin_desc cnlh_pins[] = {
	/* GPP_A */
	PINCTRL_PIN(0, "RCINB"),
	PINCTRL_PIN(1, "LAD_0"),
	PINCTRL_PIN(2, "LAD_1"),
	PINCTRL_PIN(3, "LAD_2"),
	PINCTRL_PIN(4, "LAD_3"),
	PINCTRL_PIN(5, "LFRAMEB"),
	PINCTRL_PIN(6, "SERIRQ"),
	PINCTRL_PIN(7, "PIRQAB"),
	PINCTRL_PIN(8, "CLKRUNB"),
	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
	PINCTRL_PIN(11, "PMEB"),
	PINCTRL_PIN(12, "BM_BUSYB"),
	PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
	PINCTRL_PIN(14, "SUS_STATB"),
	PINCTRL_PIN(15, "SUSACKB"),
	PINCTRL_PIN(16, "CLKOUT_48"),
	PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
	PINCTRL_PIN(18, "ISH_GP_0"),
	PINCTRL_PIN(19, "ISH_GP_1"),
	PINCTRL_PIN(20, "ISH_GP_2"),
	PINCTRL_PIN(21, "ISH_GP_3"),
	PINCTRL_PIN(22, "ISH_GP_4"),
	PINCTRL_PIN(23, "ISH_GP_5"),
	PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
	/* GPP_B */
	PINCTRL_PIN(25, "GSPI0_CS1B"),
	PINCTRL_PIN(26, "GSPI1_CS1B"),
	PINCTRL_PIN(27, "VRALERTB"),
	PINCTRL_PIN(28, "CPU_GP_2"),
	PINCTRL_PIN(29, "CPU_GP_3"),
	PINCTRL_PIN(30, "SRCCLKREQB_0"),
	PINCTRL_PIN(31, "SRCCLKREQB_1"),
	PINCTRL_PIN(32, "SRCCLKREQB_2"),
	PINCTRL_PIN(33, "SRCCLKREQB_3"),
	PINCTRL_PIN(34, "SRCCLKREQB_4"),
	PINCTRL_PIN(35, "SRCCLKREQB_5"),
	PINCTRL_PIN(36, "SSP_MCLK"),
	PINCTRL_PIN(37, "SLP_S0B"),
	PINCTRL_PIN(38, "PLTRSTB"),
	PINCTRL_PIN(39, "SPKR"),
	PINCTRL_PIN(40, "GSPI0_CS0B"),
	PINCTRL_PIN(41, "GSPI0_CLK"),
	PINCTRL_PIN(42, "GSPI0_MISO"),
	PINCTRL_PIN(43, "GSPI0_MOSI"),
	PINCTRL_PIN(44, "GSPI1_CS0B"),
	PINCTRL_PIN(45, "GSPI1_CLK"),
	PINCTRL_PIN(46, "GSPI1_MISO"),
	PINCTRL_PIN(47, "GSPI1_MOSI"),
	PINCTRL_PIN(48, "SML1ALERTB"),
	PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),

Annotation

Implementation Notes