drivers/pinctrl/intel/pinctrl-elkhartlake.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/intel/pinctrl-elkhartlake.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/intel/pinctrl-elkhartlake.c
Extension
.c
Size
16190 bytes
Lines
534
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Elkhart Lake PCH pinctrl/GPIO driver
 *
 * Copyright (C) 2019 Intel Corporation
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-intel.h"

#define EHL_PAD_OWN	0x020
#define EHL_PADCFGLOCK	0x080
#define EHL_HOSTSW_OWN	0x0b0
#define EHL_GPI_IS	0x100
#define EHL_GPI_IE	0x120

#define EHL_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)

/* Elkhart Lake */
static const struct pinctrl_pin_desc ehl_community0_pins[] = {
	/* GPP_B */
	PINCTRL_PIN(0, "CORE_VID_0"),
	PINCTRL_PIN(1, "CORE_VID_1"),
	PINCTRL_PIN(2, "VRALERTB"),
	PINCTRL_PIN(3, "CPU_GP_2"),
	PINCTRL_PIN(4, "CPU_GP_3"),
	PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
	PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
	PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
	PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
	PINCTRL_PIN(9, "I2C5_SDA"),
	PINCTRL_PIN(10, "I2C5_SCL"),
	PINCTRL_PIN(11, "PMCALERTB"),
	PINCTRL_PIN(12, "SLP_S0B"),
	PINCTRL_PIN(13, "PLTRSTB"),
	PINCTRL_PIN(14, "SPKR"),
	PINCTRL_PIN(15, "GSPI0_CS0B"),
	PINCTRL_PIN(16, "GSPI0_CLK"),
	PINCTRL_PIN(17, "GSPI0_MISO"),
	PINCTRL_PIN(18, "GSPI0_MOSI"),
	PINCTRL_PIN(19, "GSPI1_CS0B"),
	PINCTRL_PIN(20, "GSPI1_CLK"),
	PINCTRL_PIN(21, "GSPI1_MISO"),
	PINCTRL_PIN(22, "GSPI1_MOSI"),
	PINCTRL_PIN(23, "GPPC_B_23"),
	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
	/* GPP_T */
	PINCTRL_PIN(26, "OSE_QEPA_2"),
	PINCTRL_PIN(27, "OSE_QEPB_2"),
	PINCTRL_PIN(28, "OSE_QEPI_2"),
	PINCTRL_PIN(29, "GPPC_T_3"),
	PINCTRL_PIN(30, "RGMII0_INT"),
	PINCTRL_PIN(31, "RGMII0_RESETB"),
	PINCTRL_PIN(32, "RGMII0_AUXTS"),
	PINCTRL_PIN(33, "RGMII0_PPS"),
	PINCTRL_PIN(34, "USB2_OCB_2"),
	PINCTRL_PIN(35, "OSE_HSUART2_EN"),
	PINCTRL_PIN(36, "OSE_HSUART2_RE"),
	PINCTRL_PIN(37, "USB2_OCB_3"),
	PINCTRL_PIN(38, "OSE_UART2_RXD"),
	PINCTRL_PIN(39, "OSE_UART2_TXD"),
	PINCTRL_PIN(40, "OSE_UART2_RTSB"),
	PINCTRL_PIN(41, "OSE_UART2_CTSB"),
	/* GPP_G */
	PINCTRL_PIN(42, "SD3_CMD"),
	PINCTRL_PIN(43, "SD3_D0"),
	PINCTRL_PIN(44, "SD3_D1"),
	PINCTRL_PIN(45, "SD3_D2"),
	PINCTRL_PIN(46, "SD3_D3"),
	PINCTRL_PIN(47, "SD3_CDB"),
	PINCTRL_PIN(48, "SD3_CLK"),
	PINCTRL_PIN(49, "I2S2_SCLK"),
	PINCTRL_PIN(50, "I2S2_SFRM"),
	PINCTRL_PIN(51, "I2S2_TXD"),
	PINCTRL_PIN(52, "I2S2_RXD"),
	PINCTRL_PIN(53, "I2S3_SCLK"),
	PINCTRL_PIN(54, "I2S3_SFRM"),
	PINCTRL_PIN(55, "I2S3_TXD"),
	PINCTRL_PIN(56, "I2S3_RXD"),
	PINCTRL_PIN(57, "ESPI_IO_0"),
	PINCTRL_PIN(58, "ESPI_IO_1"),

Annotation

Implementation Notes